Toshiba TXZ+ Series Reference Manual page 16

f is denoted by the following formulas.
PLL
f = f × ([CGPLL0SEL]<PLL0SET[7:0]> + [CGPLL0SEL]<PLL0SET[11:8]>) ×
PLL OSC
([CGPLL0SEL] <PLL0SET[13:12]>)
Note1. The absolute value of frequency accuracy is not guaranteed.
Note2. There is no Linearity in the frequency by the fractional part Multiplication setup.
≤ (Maximum Operating Frequency)
Note3: f
PLL
f
OSC
6.00
8.00
10.00
12.00
A PLL correction can be calculated below.
= 6.0MHz, 6.0 / 0.45 = 13.33 ≈ 14
When f
OSC
The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below.
(1) It multiplies by PLL, and dividing is carried out and the target Clock frequency (f
frequency (f ).
OSC
(2) A dividing value is chosen from 1/2, 1/4, and 1/8.
(3) Moreover, set up the frequency after multiplication in the following ranges.
200MHz ≤ (f × multiplication value) ≤ 320MHz
OSC
f (MHz)
OSC
6.00
8.00
10.00
12.00
6.00
8.00
10.00
12.00
6.00
8.00
10.00
12.00
Table 1.2 PLL correction (example)
(MHz) <PLL0SET [23:17]> (a decimal, an integral value)
Table 1.3 PLL0SET set point (example)
Multiplication Dividing
value
40.0000
30.0000
24.0000
20.0000
53.3125
40.0000
32.0000
26.6250
53.3125
40.0000
32.0000
26.6250
Clock Control and Operation Mode
14
18
23
27
; A fractional part is rounded up.
f (MHz)
PLL
value
1/2 120.00
1/2 120.00
1/2 120.00
1/2 120.00
1/4 79.97
1/4 80.00
1/4 80.00
1/4 79.88
1/8 39.98
1/8 40.00
1/8 40.00
1/8 39.94
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TXZ+ Family
TMPM3H Group(1)
) is generated for input
PLL
<PLL0SET[23:0]>
0x1C1028
0x24501E
0x2E9018
0x36D014
0x1C2535
0x246028
0x2EA020
0x36EA1A
0x1C3535
0x247028
0x2EB020
0x36FA1A
2022-05-10
Rev. 1.3