A Reset Factor And The Reset Initialized Range - Toshiba TXZ+ Series Reference Manual

3.2.7.1. A reset factor and the reset initialized range

A reset factor and the range initialized are shown in Table 3.1.
Registers and
peripheral function
Reset
signal
name
[RTCSECR]
[RTCMINR]
[RTCHOURR]
[RTCDAYR]
[RTCDATER]
[RTCMONTHR]
RTC
[RTCYEARR]
[RTCADJCTL]
[RTCADJDAT]
[RTCADJSIGN]
[RTCPAGER] (Note2)
Others
[RLMSHTDNOP]
[RLMPROTECT]
Low speed
oscillation [RLMLOSCCR]
power control
[RLMRSTFLG0]
reset flag [RLMRSTFLG1]
[RLMGPREG]
[IAIMCxx]
Interrupt [IANIC00]
control [IBIMCxxx]
[IBNIC00]
Flash [FCSBMR]
Port All the register
LCD (Note3)
OFD
LVD
Debugging interface
Others
: It is initialized
×: It is not initialized
Note1: When reset is performed, the data of on-chip RAM will not be guaranteed.
Note2: [RTCPAGER]<ENATMR><ENAALM> are not initialized. Other symbols are initialized.
Note3: [DLCDBUFn] display buffers are not initialized.
Note4: Reset area when releasing STOP2 mode by LVD reset is as same as reset area released by the warm-
reset.
Note5: Debug interface and [FCSBMR] in Flash are not initialized by the reset in NORMAL, IDLE, or STOP2
mode. But, they are initialized by the reset in STOP1mode.
Table 3.1 A reset factor and the initialized range
STOP2 mode Cold
release reset
Reset
Interrupt pin POR
factor (Note1) (Note1)
(Note4)
STOP2
RESET_N PORHV RESET_N
REQ
× × ×
 
×
 
×

× ×
 
×
  
  
  
 
×
  
 
×
  
  
Clock Control and Operation Mode
Reset factors
RESET_N OFD WDT
pin reset reset
OFD WDT
RSTOUT RSTOUT
× × ×
  
  
× × ×
  
  
×
× ×
(Note5)
  
  
  

× ×
×
× ×
(Note5)
  
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TXZ+ Family
TMPM3H Group(1)
Warm reset (Note1)
LVD PORF <SYSRES
reset reset ETREQ>
LVD PORF
RESET
RSTOUT RESET
× ×
 
 
×
×
 
 
×

(Note5)
 
 
 
×
×
×

(Note5)
 
CPU
CPU
LOCKUP
reset
reset
SYS LOCKUP
RESET
REQ REQ
× ×
 
 
× ×
 
 
× ×
 
 
 
× ×
× ×
 
2022-05-10
Rev. 1.3