Cgfsysmenb] (Clock Supply And Stop Register B For Fsysm) - Toshiba TXZ+ Series Reference Manual

1.4.2.9. [CGFSYSMENB] (Clock supply and stop register B for fsysm)

Bit Bit Symbol
31 IPMENB31
30 IPMENB30
29 IPMENB29
28 IPMENB28
27 IPMENB27
26 IPMENB26
25 IPMENB25
24 IPMENB24
23 IPMENB23
22 IPMENB22
21 IPMENB21
20 IPMENB20
19 IPMENB19
18 IPMENB18
17 IPMENB17
16 IPMENB16
15 IPMENB15
14 IPMENB14
13 IPMENB13
12 IPMENB12
11 IPMENB11
10 IPMENB10
9 IPMENB09
8 IPMENB08
7 IPMENB07
6 IPMENB06
5 IPMENB05
4 IPMENB04
3 IPMENB03
2 IPMENB02
1 IPMENB01
0 IPMENB00
Note1: Even if the initial value of a register is set to stop of the clock, the clock is supplied to the register during
the reset.
Note2: Please write "0" into the unavailable register bits in the TMPM3HP, TMPM3HM, TMPM3HN, and
TMPM3HL. For detail, refer to "1.5. Information according to product".
After
Type
reset
0 R Read as "0".
0 R Read as "0".
0
R Read as "0".
0
R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
Enable the clock of EI2C ch3
0 R/W 0: Clock stop
1: Clock supply
Enable the clock of EI2C ch2
0 R/W 0: Clock stop
1: Clock supply
Enable the clock of EI2C ch1
0 R/W 0: Clock stop
1: Clock supply
Enable the clock of EI2C ch0
0 R/W 0: Clock stop
1: Clock supply
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
0 R Read as "0".
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TMPM3H Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2022-05-10
Rev. 1.3