Toshiba TXZ+ Series Reference Manual page 3

1.3.4.1. NORMAL → IDLE → NORMAL Operation mode transition ........................................................................................... 33
1.3.4.2. NORMAL → STOP1 → NORMAL Operation mode transition ....................................................................................... 33
1.3.4.3. NORMAL → STOP2 → RESET → NORMAL Operation mode transition ...................................................................... 34
1.4. Explanation of register ..................................................................................................................................... 35
1.4.1. Register list ................................................................................................................................................................. 35
1.4.1.1. Clock and mode control ................................................................................................................................................. 35
1.4.1.2. Low speed oscillation/power control (Note) ................................................................................................................... 35
1.4.2. Register description .................................................................................................................................................... 36
1.4.2.1. [CGPROTECT] (CG write protection register) ............................................................................................................... 36
1.4.2.2. [CGOSCCR] (Oscillation control register) ...................................................................................................................... 36
1.4.2.3. [CGSYSCR] (System clock control register) .................................................................................................................. 37
1.4.2.4. [CGSTBYCR] (Standby control register) ....................................................................................................................... 38
1.4.2.5. [CGSCOCR] (SCOUT Output control register) .............................................................................................................. 38
1.4.2.6. [CGPLL0SEL] (PLL selection register for fsys) .............................................................................................................. 39
1.4.2.7. [CGWUPHCR] (High speed oscillation warming up register) ......................................................................................... 39
1.4.2.8. [CGWUPLCR] (Low speed oscillation warming up register) .......................................................................................... 40
1.4.2.9. [CGFSYSMENB] (Clock supply and stop register B for fsysm) ...................................................................................... 41
1.4.2.10. [CGFSYSENA] (Clock supply and stop register A for fsys).......................................................................................... 42
1.4.2.11. [CGFSYSENB] (Clock supply and stop register B for fsys).......................................................................................... 44
1.4.2.12. [CGFCEN] (Clock supply and stop register for fc) ....................................................................................................... 46
1.4.2.13. [CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit) ............................................................... 46
1.4.2.14. [RLMLOSCCR] (Low speed oscillation control register) .............................................................................................. 46
1.4.2.15. [RLMSHTDNOP] (Power supply cut off control register) ............................................................................................. 46
1.4.2.16. [RLMPROTECT] (RLM write protection register) ......................................................................................................... 47
1.5. Information according to product ..................................................................................................................... 48
1.5.1. [CGFSYSMENB] ........................................................................................................................................................ 48
1.5.2. [CGFSYSENA] ........................................................................................................................................................... 49
1.5.3. [CGFSYSENB] ........................................................................................................................................................... 50
2. Memory Map ............................................................................................................................................... 51
2.1. Overview .......................................................................................................................................................... 51
2.1.1. TMPM3HxFDA .......................................................................................................................................................... 52
2.1.2. TMPM3HxFZA .......................................................................................................................................................... 53
2.1.3. TMPM3HxFYA .......................................................................................................................................................... 54
2.2. Bus Matrix ........................................................................................................................................................ 55
2.2.1. Structure ..................................................................................................................................................................... 55
2.2.1.1. Single chip mode ........................................................................................................................................................... 55
2.2.1.2. Single boot mode .......................................................................................................................................................... 56
2.2.2. Connection table ......................................................................................................................................................... 57
2.2.2.1. Code area/ SRAM area ................................................................................................................................................. 57
2.2.2.2. Peripheral area .............................................................................................................................................................. 58
3. Power Supply and Reset Operation ........................................................................................................... 59
3.1. Outline .............................................................................................................................................................. 59
3.2. Function and Operation ................................................................................................................................... 60
3.2.1. Cold reset ................................................................................................................................................................... 60
3.2.1.1. Reset by a Power On Reset Circuit (without using a RESET_N pin) ............................................................................. 61
Clock Control and Operation Mode
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TXZ+ Family
TMPM3H Group(1)
2022-05-10
Rev. 1.3