Stop2 Mode Transition Flow - Toshiba TXZ+ Series Reference Manual

1.3.2.3. STOP2 mode transition flow

Set up the following procedure at switching to STOP2.
Because STOP2 mode is released by an interrupt, set the interrupt before switching to STOP2 mode. For the
interrupts that can be used to release the STOP2 mode, refer to "1.3.3.1. The release source of a Low Power
Consumption mode". Disables unused interrupts and unavailable interrupts for release STOP2.
1 [SIWDxEN]<WDTE> = 0
2 [SIWDxCR]<WDCR[7:0]> = 0xB1
3 [FCSR0]<RDYBSY> is read.
[RLMSHTDNOP]<PTKEEP> = 1
4
5 [CGSTBYCR]<STBY[1:0]> = 10
6 [CGPLL0SEL]<PLL0SEL> = 0
7 [CGPLL0SEL]<PLL0ST> is read
8 [CGPLL0SEL]<PLL0ON> = 0
[CGWUPHCR]<WUCLK> = 0
9
[CGWUPHCR]<WUPT[15:4]> = 0x03C
10 [CGOSCCR]<IHOSC1EN> = 1
11 [CGWUPHCR]<WUON> = 1
12 [CGWUPHCR]<WUEF> is read.
[CGOSCCR]<OSCSEL> = 0
13
14 [CGOSCCR]<OSCF> is read
15 [CGOSCCR]<EOSCEN[1:0]> = 00
16 [CGOSCCR]<IHOSC2EN> = 0
17 [CGOSCCR]<EOSCEN[1:0]> is read
18 [CGOSCCR]<IHOSC2F> is read
[RLMRSTFLG0]<STOP2RSTF> = 0
19
[RLMRSTFLG0]< PINRSTF> = 0
WFI command execution
20
21 Jump instruction
Note1: Refer to the reference manual "Exception" for a reset flag register [RLMRSTFLG0].
Note2: When using the A mode of SIWDT, step 1, 2, 16 and 18 are not required.
Switching procedure (from NORMAL mode)
Disable SIWDT.
Disable SIWDT.
Wait until Flash becomes the Ready state (= 1).
IO control signal is made to hold.
Low Power Consumption mode selection is set to STOP2.
Select the PLL for fsys to "PLL is unused (f
Wait until the PLL selection status for fsys becomes PLL unused. (= 0).
Stop PLL for fsys.
Set the warming-up clock selection to internal high speed oscillator 1
(IHOSC1).
Set the high speed oscillation warming-up timer setting value of 163.4
μs (= 0x03C) or more.
Enable the internal high speed oscillator 1.
Start the high speed oscillation warming-up timer
Wait until the warming-up timer status flag becomes ends (= 0).
Set the high speed oscillation selection for f
oscillator1 (IHOSC1).
Wait until the high speed oscillation selection status for f
internal high speed oscillator1 (IHOSC1) (= 0).
Set the selection of an external oscillator operation to unused.
The internal high speed oscillator 2 is stopped.
The register writing of 15th row is checked (= 00).
Wait until the internal oscillation stable flag of the internal high speed
oscillator 2 becomes zero.
A STOP2 reset flag/reset pin flag is cleared (Note1).
Switch to STOP2.
Return to 20.
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TMPM3H Group(1)
Clock Control and Operation Mode
)".
OSC
to internal high speed
OSC
TXZ+ Family
becomes
OSC
2022-05-10
Rev. 1.3