Bus Matrix; Structure; Single Chip Mode; Figure 2.4 Single Chip Mode - Toshiba TXZ+ Series Reference Manual

2.2. Bus Matrix

This MCU contains two bus masters such as a CPU core and DMA controllers.
Bus masters connect to slave ports (S0 to S4) of Bus Matrix. In the bus matrix, master ports (M0 to M14) connect
to peripheral functions via connections described as (o) or (●) in the following figure. (●) shows a connection to a
mirror area.
While multiple slaves are connected on the same bus master line in the Bus Matrix, if multiple slave accesses are
generated at the same time, a priority is given to access from a master with the smallest slave number.

2.2.1. Structure

2.2.1.1. Single chip mode

Code Flash
Data Flash
RAM0
RAM1
RAM2
Backup RAM
Boot ROM
TSPI (ch0/1)
I2C, EI2C (ch0)
UART (ch0/1/2/3)
T32A (ch0/1/2/3)
TSPI (ch2/3/4)
I2C, EI2C (ch1/2/3)
UART (ch4/5/6/7)
T32A (ch4/5/6/7)
CRC
DMAC (SFR)
SIWDT
TRGSEL
DNF
RAMP (SFR)
DMAC
(unitB)
DMAC
(unitA)
S0 S1
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
APB
M12
APB
M13
APB
M14
S0 S1

Figure 2.4 Single chip mode

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Clock Control and Operation Mode
Cortex-M3
System
Data
Instruction
S2 S3 S4
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
S2 S3 S4
TXZ+ Family
TMPM3H Group(1)
GPREG
LCD
IA (INTIF)
I2CS
RLM
LVD
AO
APB
ADC
DAC
COMP
IO
CG
IB (INTIF)
IMN
PORT
A-PMD
A-ENC
RMC
RTC
OFD
Flash (SFR)
TRM
2022-05-10
Rev. 1.3