Fujitsu F2MC-16L Hardware Manual page 51

Table 3.2-2 Settings for subclock selection
Subclock
(*1)
Availability Source
the evaluation MCU
Available Clock area PGA
299
PGA
256
Not
available
*1: Clock oscillation with a crystal unit mounted in the user system is not supported.
*2: In the table, PGA299 and PGA256 indicate different adapter boards, which are:
PGA299: Adapter board for the PGA-299P
PGA256: Adapter board for the PGA-256P
The correspondence between subclock signals (X0A and X1A) and pin numbers on the evaluation MCU depends on the
evaluation MCU used. Check the correspondence before making settings.
For more information on the correspondence between subclock signals and pin numbers on the evaluation MCU,
contact the Fujitsu Sales Dept. or Support Dept.
Note:
To supply the main clock signal from the user system, add an oscillation circuit to the user
system and have the main clock supplied via a CMOS buffer.
Table 3.2-1 Settings for main clock selection
Main clock source
Clock area
User system
FC SEL
setting
Pin corresponding to
3
(*2)
X1A: Pin No. 267 OFF
X0A: Pin No. 217
X1A: Pin No. 217 OFF
X0A: Pin No. 267
X1A: Pin No. 51 OFF
X0A: Pin No. 176
X1A: Pin No. 176 OFF
X0A: Pin No. 51
ON
-
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FC SEL setting
1 2
OFF OFF
ON ON
SUB XTAL setting
4
OFF X1A:B connected to X1A:C
(a) in Figure 3.2-3
OFF X1A:B connected to X0A:B
(b) in Figure 3.2-3
OFF X1A:B connected to X1A:C
(a) in Figure 3.2-3
OFF X1A:B connected to X0A:B
(b) in Figure 3.2-3
ON X1A:A connected to X1A:B
(c) in Figure 3.2-3
3.2 Clock Supply
X0A:B connected to X0A:C
(a) in Figure 3.2-3
X1A:C connected to X0A:C
(b) in Figure 3.2-3
X0A:B connected to X0A:C
(a) in Figure 3.2-3
X1A:C connected to X0A:C
(b) in Figure 3.2-3
X0A:A connected to X0A:B
(c) in Figure 3.2-3
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