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Fujitsu F2MC-16LX Series Manuals
Manuals and User Guides for Fujitsu F2MC-16LX Series. We have
13
Fujitsu F2MC-16LX Series manuals available for free PDF download: Hardware Manual, Operation Manual, Application Note, User Manual
Fujitsu F2MC-16LX Series Hardware Manual (706 pages)
16-bit Microcontroller MB90330 series
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 13.48 MB
Table of Contents
Table of Contents
9
Chapter 1 Overview
17
Feature of MB90330 Series
18
Block Diagram
23
Package Dimension
24
Pin Assignment
26
Pin Function
27
I/O Circuit Types
34
Handling of Device
37
Chapter 2 Cpu
41
Outline Specification of CPU
42
Memory Space
43
Register of CPU
48
Accumulator (A)
50
User Stack Pointer (USP) and System Stack Pointer (SSP)
51
Processor Status (PS)
52
Program Counter (PC)
55
Program Bank Register (PCB)
56
Direct Page Register (DPR)
57
General-Purpose Registers (Register Bank)
58
Prefix Code
59
Chapter 3 Interrupt
63
Outline of Interrupt
64
Interrupt Cause and Interrupt Vector
67
Interrupt Control Register and Peripheral Function
70
Interrupt Control Registers (ICR00 to ICR15)
72
Interrupt Control Register Functions
74
Hardware Interrupt
77
Operation of Hardware Interrupt
80
Operation Flow of Hardware Interrupt
82
Procedure for Using a Hardware Interrupt
83
Multiple Interrupts
84
Hardware Interrupt Processing Time
86
Software Interrupt
88
Interrupts by Extended Intelligent I/O Service (EI 2 OS)
90
Extended Intelligent I/O Service
92
OS) Descriptor (ISD)
92
Each Register of Extended Intelligent I/O Service
94
OS) Descriptor (ISD)
94
Operation of Extended Intelligent I/O Service (EI 2 OS)
97
Procedure for Use of Extended Intelligent I/O Service (EI 2 OS)
98
OS) Processing Time
99
Exception Processing Interrupt
102
Interruption by Μdmac
103
Μdmac Function
104
Register of Μdmac
105
DMA Descriptor Channel Specification Register (DCSR)
106
DMA Status Register (DSRH/DSRL)
108
DMA Stop Status Register (DSSR)
109
DMA Permission Register (DERH/DERL)
110
DMA Descriptor Window Register (DDWR)
111
DMA Data Counter (DDCTH/DDCTL)
112
DMA I/O Register Address Pointer (DIOAH/DIOAL)
113
DMA Control Register (DMACS)
114
DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)
116
Explanation of Operation of Μdmac
117
Exceptions
119
Stack Operation of Interrupt Processing
120
Program Example of Interrupt Processing
122
Delayed Interrupt Generation Module
126
Operation of Delayed Interrupt Generation Module
127
Chapter 4 Reset
129
Outline of Reset
130
Reset Factors and Oscillation Stabilization Wait Times
132
External Reset Pin
134
Reset Operation
135
Reset Factor Bit
137
State of each Pin at Reset
139
Chapter 5 Clock
141
Outline of Clock
142
Block Diagram of Clock Generation Section
145
Clock Select Register (CKSCR)
148
Clock Mode
151
Oscillation Stabilization Wait Time
154
Connection of Oscillator and External Clock
155
Chapter 6 Low-Power Consumption Mode
157
Outline of Low-Power Consumption Mode
158
Block Diagram of Low-Power Consumption Control Circuit
161
Low-Power Consumption Mode Control Register (LPMCR)
163
CPU Intermittent Operation Mode
166
Standby Mode
167
Sleep Mode
168
Timebase Timer Mode
170
Watch Mode
172
Stop Mode
174
State Transition Diagram
176
State of the Pin During Standby Mode, Hold, and Reset
178
Precautions When Using Low-Power Consumption Mode
188
Chapter 7 Mode Setting
191
Mode Setting
192
Mode Pins (MD2 to MD0)
193
Mode Data
194
External Memory Access
198
Automatic Ready Function Selection Register (ARSR)
200
External Address Output Control Register (HACR)
201
Bus Control Signal Selection Register (EPCR)
202
Operation in each Mode of Mode Setting
204
External Memory Access Control Signal
205
Ready Function
208
Holding Function
211
Chapter 8 I/O Port
213
Functions of I/O Ports
214
I/O Port Register
215
Port Data Register (PDR0 to PDRB)
216
Port Direction Register (DDR0 to DDRB)
217
Other Registers
218
Chapter 9 Timebase Timer
221
Overview of Timebase Timer
222
Configuration of Timebase Timer
224
Timebase Timer Control Register (TBTC)
226
Interrupt of Timebase Timer
228
Operations of Timebase Timer
229
Precautions When Using Timebase Timer
231
Program Example of Timebase Timer
233
Chapter 10 Watchdog Timer
235
Overview of Watchdog Timer
236
Watchdog Timer Control Register (WDTC)
238
Configuration of Watchdog Timer
240
Operations of Watchdog Timer
242
Precautions When Using Watchdog Timer
244
Program Examples of Watchdog Timer
245
Chapter 11 Watch Timer
247
Overview of Watch Timer
248
Configuration of Watch Timer
249
Watch Timer Control Register (WTC)
250
Operation of Watch Timer
252
Advertisement
Fujitsu F2MC-16LX Series Hardware Manual (710 pages)
16 Bit, Controller Manual
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 12.52 MB
Table of Contents
Table of Contents
11
Chapter 1 Overview
19
Features of the MB90895 Series
20
Product Lineup for MB90895 Series
22
Block Diagram of MB90895 Series
25
Pin Assignment
26
Package Dimensions
27
Pin Description
28
I/O Circuit
31
Chapter 2 Handling Devices
33
Precautions When Handling Devices
34
Chapter 3 Cpu
37
Memory Space
38
Mapping of and Access to Memory Space
40
Memory Map
42
Addressing
43
Linear Addressing
44
Bank Addressing
45
Allocation of Multi-Byte Data in Memory
47
Dedicated Registers
49
Dedicated Registers and General-Purpose Register
51
Accumulator (A)
52
Stack Pointer (USP, SSP)
55
Processor Status (PS)
58
Program Counter (PC)
63
Direct Page Register (DPR)
64
Bank Register (PCB, DTB, USB, SSB, and ADB)
65
General-Purpose Register
66
Prefix Code
68
Bank Select Prefix (PCB, DTB, ADB, and SPB)
69
Common Register Bank Prefix (CMR)
71
Flag Change Inhibit Prefix (NCC)
72
Restrictions on Prefix Code
73
Interrupt
75
Interrupt Factor and Interrupt Vector
77
Interrupt Control Registers and Peripherals
80
Interrupt Control Register (ICR00 to ICR15)
82
Function of Interrupt Control Register
84
Hardware Interrupt
87
Operation of Hardware Interrupt
90
Procedure for Use of Hardware Interrupt
92
Multiple Interrupts
93
Software Interrupt
95
Interrupts by Extended Intelligent I/O Service (EI 2 OS)
96
EI os Descriptor (ISD)
98
Each Register of EI 2 os Descriptor (ISD)
100
Operation of EI 2 os
103
Procedure for Use of EI 2 os
104
EI 2 os Processing Time
105
Exception Processing Interrupt
107
Time Required to Start Interrupt Processing
108
Stack Operation for Interrupt Processing
110
Program Example of Interrupt Processing
111
Reset
114
Reset Factors and Oscillation Stabilization Wait Times
116
External Reset Pin
118
Reset Operation
119
Reset Factor Bit
121
State of each Pin at Reset
124
Clock
125
Block Diagram of Clock Generation Section
128
Register in Clock Generation Section
130
Clock Select Register (CKSCR)
131
Pll/Subclock Control Register (PSCCR)
134
Clock Mode
136
Oscillation Stabilization Wait Time
140
Connection of Oscillator and External Clock
141
Low-Power Consumption Mode
142
Block Diagram of Low-Power Consumption Circuit
145
Registers for Setting Low-Power Consumption Modes
147
Low-Power Consumption Mode Control Register (LPMCR)
148
CPU Intermittent Operation Mode
151
Standby Mode
152
State Transition in Standby Mode
163
Pin State in Standby Mode, at Reset
164
Precautions When Using Low-Power Consumption Mode
165
CPU Mode
169
Mode Pins (MD2 to MD0)
170
Mode Data
172
Memory Access Mode
174
Operations for Selecting Memory Access Mode
175
Chapter 4 I/O Port
177
Overview of I/O Ports
178
Registers of I/O Port and Assignment of Pins Serving as External Bus
179
Port 1
180
Registers for Port 1 (PDR1, DDR1)
182
Operation of Port 1
183
Port2
185
Registers for Port 2 (PDR2, DDR2)
188
Operation of Port 2
189
Port 3
191
Registers for Port 3 (PDR3, DDR3)
193
Operation of Port 3
194
Port 4
196
Registers for Port 4 (PDR4, DDR4)
198
Operation of Port 4
199
Port 5
201
Registers for Port 5 (PDR5, DDR5, ADER)
204
Operation of Port 5
206
Port Input Level Select Register
208
CHAPTER 5 Timebase Timer
209
Overview of Timebase Timer
210
Block Diagram of Timebase Timer
212
Configuration of Timebase Timer
214
Timebase Timer Control Register (TBTC)
215
Interrupt of Timebase Timer
217
Explanation of Operations of Timebase Timer Functions
218
Precautions When Using Timebase Timer
222
Program Example of Timebase Timer
223
CHAPTER 6 Watchdog Timer
225
Overview of Watchdog Timer
226
Configuration of Watchdog Timer
227
Watchdog Timer Registers
229
Watchdog Timer Control Register (WDTC)
230
Explanation of Operations of Watchdog Timer Functions
232
Precautions When Using Watchdog Timer
235
Program Examples of Watchdog Timer
236
CHAPTER 7 16-Bit I/O Timer
237
Overview of 16-Bit Input/Output Timer
238
Block Diagram of 16-Bit Input/Output Timer
239
Block Diagram of 16-Bit Free-Run Timer
240
Block Diagram of Input Capture
242
Configuration of 16-Bit Input/Output Timer
244
Timer Counter Control Status Register (TCCS)
247
Timer Counter Data Register (TCDT)
249
Input Capture Control Status Registers (ICS01, ICS23)
251
Input Capture Data Registers (IPCP0 to IPCP3)
253
Interrupts of 16-Bit Input/Output Timer
254
Explanation of Operation of 16-Bit Free-Run Timer
255
Explanation of Operation of Input Capture
257
Precautions When Using 16-Bit Input/Output Timer
260
Program Example of 16-Bit Input/Output Timer
261
Fujitsu F2MC-16LX Series Hardware Manual (395 pages)
16-Bit Microcontrollers
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 3.4 MB
Table of Contents
Table of Contents
5
Chapter 1 Overview
21
Features
21
Product Lineup
23
Table 1.2A MB90580 Series Product Lineup
23
Block Diagram
24
Chapter 1 Overview
24
Figure 1.3A Block Diagram of MB90580 Series
24
Pin Assignment
25
SQFP-100 Pin Assignment
25
Figure 1.4A Pin Assignment of MB90580 (LQFP-100)
25
Pin Assignment
26
Figure 1.4B Pin Assignment of MB90580 (QFP-100)
26
Pin Functions
27
Table 1.5A Pin Functions (1/4) (STBC: with Standby Control)
27
Table 1.5B Pin Functions (2/4)
28
Table 1.5C Pin Functions (3/4)
29
Table 1.5D Pin Functions (4/4)
30
Table 1.5E I/O Circuit Format (1)
31
Table 1.5F I/O Circuit Format (2)
32
Table 1.5G I/O Circuit Format (3)
33
Figure 1.6A Using External Clock
34
Figure 1.6B Connection of Power Pins
34
Handling the Device
34
Chapter 2 CPU
35
Cpu
35
Memory Space
36
Figure 2.1.1A Sample Relationship between F2MC-16LX System and Memory Map
36
Figure 2.1.1B Sample Linear Addressing
37
Figure 2.1.1C Physical Addresses of each Space
38
Table 2.1.1A Default Space
38
Figure 2.1.1D Sample Allocation of Multi-Byte Data in Memory
39
Figure 2.1.1E Execution of MOVW A, 080FFFFH
39
Registers
40
Figure 2.1.2A Special Registers
40
Figure 2.1.2B General-Purpose Registers
41
Figure 2.1.2C Program Counter
41
Figure 2.1.2D 32-Bit Data Transfer
42
Figure 2.1.2E AL-AH Transfer
42
Figure 2.1.2F Stack Manipulation Instruction and Stack Pointer
43
Figure 2.1.2G PS Structure
44
Figure 2.1.2H Condition Code Register Configuration
44
Figure 2.1.2I Register Bank Pointer
45
Figure 2.1.2J Interrupt Level Register
45
Chapter 2 CPU
45
Table 2.1.2A Levels Indicated by the Interrupt Level Mask (ILM) Register
45
Table 2.1.2B Register Functions
46
Table 2.1.2C Relationship between Registers
46
Figure 2.1.2K Generating a Physical Address in Direct Addressing Mode
47
Prefix Codes
48
Table 2.1.3A Bank Select Prefix
48
Figure 2.1.3A Interrupt Disable Instruction
49
Figure 2.1.3B Interrupt Disable Instructions and Prefix Codes
50
Figure 2.1.3C Consecutive Prefix Codes
50
Chapter 3 Memory
51
Memory Access Modes
51
Table 3.1A Memory Access Mode
51
Mode Pins
52
Table 3.1.1A Mode Pins and Modes
52
Mode Data
53
Bus Mode
54
Figure 3.1.3A Access Areas and Physical Addresses in each Bus Mode
54
Chapter 3 Memory
55
Table 3.1.3A Sample Recommended Setting of Mode Pins and Mode Data
55
Table 3.1.3B Modes and Related External Pin Operations
55
External Memory Access
56
Block Diagram
56
Figure 3.2.1A External Bus Pin Control Circuit
56
Registers and Register Details
57
Table 3.2.0A Selecting the High-Order Address Bit Output Control
59
Operations
62
Figure 3.2.1A External Memory Access Timing Chart
62
Figure 3.2.1B External Memory Access Timing Chart
63
Figure 3.2.1C Ready Timing Chart
64
Figure 3.2.1D Hold Timing
65
Chapter 4 Clock and Reset
67
Clock Generator
67
Figure 4.1A Clock Generator Circuit Block Diagram
67
Reset Causes
68
Table 4.2A Reset Causes
68
Figure 4.2A Reset Cause Bit Block Diagram
69
Figure 4.2B WDTC (Watch-Dog Timer Control Register)
69
Table 4.2B Reset Cause Bits
69
Operation after Reset Release
70
Figure 4.3A Source and Destination of Reset Vector and Mode Data
70
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions
71
Outline
71
Block Diagram
72
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions
72
Figure 5.2A Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram
72
Registers and Register Details
73
WDTC (Watch-Dog Timer Control Register)
74
Table 5.3.1A Reset Cause Registers
74
Table 5.3.1B Watchdog Timer Interval Selection Bits
75
TBTC (Time Base Timer Control Register)
76
Table 5.3.2A Selecting the Time Base Timer Interval
76
Watch Timer Control Register (WTC)
77
Table 5.3.3A Watch Timer Interval Selection
78
Operation
79
Watch-Dog Timer
79
Figure 5.4.1A Watch-Dog Timer Operation
79
Time Base Timer
80
Watch Timer
80
Chapter 6 Low Power Control Circuit
81
Outline
81
Block Diagram
82
Figure 6.2A Low-Power Consumption Control Circuit and Clock Generator
82
Chapter 6 Low Power Control Circuit
83
Registers and Register Details
83
LPMCR (Low Power Mode Control Register)
83
Table 6.3.1A CG Bit Setting
84
CKSCR (Clock Selection Register)
85
Table 6.3.2A WS Bit Settings
85
Table 6.3.2B CS Bit Settings
86
Operations
87
Table 6.4A Low Power Consumption Mode Operating Statuses
87
Pseudo-Watch Mode
88
Sleep Mode
88
Stop Mode
89
Watch Mode
89
CPU Intermittent Operation Function
90
Hardware Standby Mode
90
Setting the Main Clock Oscillation Stabilization Waiting Period
91
Switching the Machine Clock
91
Figure 6.4.8A Clock Selection State Transition Diagram (1)
92
Figure 6.4.8B Clock Selection State Transition Diagram (2)
93
State Transition
93
Table 6.4.9A List of Transition Conditions
94
Chapter 7 Interrupt
96
Figure 6.4.9A Low Power Consumption Mode Transition Diagram a
97
Figure 6.4.9B Low Power Consumption Mode Transition Diagram B
98
Figure 6.4.9C Low Power Consumption Mode Transition Diagram C
99
Figure 6.4.9D Low Power Consumption Mode Transition Diagram D
100
Chapter 7 Interrupt
101
Outline
101
Causes of Interrupt
102
Table 7.2A Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
102
Interrupt Vector
103
Table 7.3A MB90580 Interrupt Assignment Table (1/2)
103
Hardware Interrupt
104
Overview
104
Structure
104
Operation
104
Figure 7.4.3A Occurrence and Release of Hardware Interrupt
105
Figure 7.4.3B Hardware Interrupt Operation Flow
106
Table 7.4.3A Compensation Values for Interrupt Processing Cycle Count
106
Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed
107
Interrupt Inhibit Instruction
107
Multiple Interrupts
107
Register Saving in Stack Upon Interrupt
107
Precaution in Using Hardware Interrupt
107
Figure 7.4.7A Registers Saved in Stack
107
Software Interrupt
108
Overview
108
Structure
108
Operation
109
Others
109
Figure 7.5.3A Occurrence and Release of Software Interrupt
109
Extended Intelligent I/O Service (EI2OS)
110
Overview
110
Figure 7.6.1A Outline of Extended Intelligent I/O Service
110
Structure
111
Table 7.6.2A ICS Bits, Channel Numbers, and Descriptor Addresses
112
Table 7.6.2B S Bits and End Conditions
112
Table 7.6.2C Interrupt Level Setting Bits and Interrupt Levels
113
Figure 7.6.2A Extended Intelligent I/O Service Descriptor Configuration
114
Operation
117
Figure 7.6.3A EI2OS Operation Flow
117
Figure 7.6.3B EI2OS Use Flow
118
EI2OS Execution Time
119
Table 7.6.4A Execution Time When the Extended I2OS Continues
119
Table 7.6.4B Data Transfer Compensation Values for Extended I2OS Execution Time
119
Exceptions
120
Exception Due to Execution of an Undefined Instruction
120
Chapter 8 Parallel Ports
121
Outline
121
Block Diagram
122
Figure 8.2A Block Diagram of I/O Port
122
Figure 8.2B Block Diagram of Input Resistor Register
122
Figure 8.2C Block Diagram of Output Pin Register
122
Registers and Register Details
123
Figure 8.3A Registers of Parallel Ports
123
Port Data Register
124
Port Direction Registers
125
Input Resistor Register
126
Output Pin Register
126
Analogue Input Enable Register
127
Low Noise Output Select Register
127
Chapter 9 Dtp/External Interrupt
129
Outline
129
Block Diagram
129
Figure 9.2A Block Diagram of Dtp/External Interrupt
129
Registers and Register Details
130
Interrupt/Dtp Enable Register (ENIR: Enable Interrupt Request Register)
130
Interrupt/Dtp Cause Register (EIRR: External Interrupt Request Register)
131
Request Level Setting Register (ELVR: External Level Register)
131
Operations
132
External Interrupts
132
Figure 9.4.1A External Interrupt
132
DTP Operation
133
Figure 9.4.2A Timing to Cancel the External Interrupt at the End of DTP Operation
133
Figure 9.4.2B Sample Interface to the External Peripheral
133
Switching between External Interrupt and DTP Requests
134
Figure 9.4.3A Switching between External Interrupt and DTP Requests
134
Notes on Use
135
Conditions on the Externally Connected Peripheral When DTP Is Used
135
Recovery from Standby
135
External Interrupt/Dtp Operation Procedure
135
External Interrupt Request Level
135
Figure 9.5.4A Clearing the Cause Hold Circuit Upon Level Set
135
Figure 9.5.4B Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts Are Enabled
135
Advertisement
Fujitsu F2MC-16LX Series Hardware Manual (635 pages)
16-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 7.23 MB
Table of Contents
Table of Contents
10
Chapter 1 Overview
22
Feature of MB90335 Series
23
Block Diagram
28
Package Dimension
29
1.4 Pin Assignment
30
Pin Function
31
I/O Circuit Types
34
Handling of Device
37
Chapter 2 Cpu
40
Overview of the CPU
41
Memory Space
42
Linear Addressing
45
Bank Addressing
46
Multibyte Data in Memory Space
48
Registers
49
Accumulator (A)
52
User Stack Pointer (USP) and System Stack Pointer (SSP)
53
Processor Status (PS)
54
Program Counter (PC)
57
Bank Registers (PCB, DTB, USB, SSB, ADB)
58
Direct Page Register (DPR)
59
Register Bank
60
Prefix Codes
61
Interrupt Disable Instructions
64
Chapter 3 Interrupt
66
Outline of Interrupt
67
Interrupt Cause and Interrupt Vector
70
Interrupt Control Register and Peripheral Function
73
Interrupt Control Registers (ICR00 to ICR15)
75
Interrupt Control Register Functions
77
Hardware Interrupt
80
Operation of Hardware Interrupt
83
Operation Flow of Hardware Interrupt
85
Procedure for Using a Hardware Interrupt
86
Multiple Interrupts
87
Hardware Interrupt Processing Time
89
Software Interrupt
91
Interrupts by Extended Intelligent I/O Service (EI 2 OS)
93
Extended Intelligent I/O Service (EI 2 OS) Descriptor (ISD)
95
OS) Descriptor (ISD)
97
Operation of Extended Intelligent I/O Service (EI 2 OS)
100
Procedure for Use of Extended Intelligent I/O Service (EI 2 OS)
101
Extended Intelligent I/O Service (EI 2 OS) Processing Time
102
Exception Processing Interrupt
105
Interruption by Μdmac
106
Μdmac Function
107
Register of Μdmac
108
DMA Descriptor Window Register (DDWR)
115
Explanation of Operation of Μdmac
121
Exceptions
123
Stack Operation of Interrupt Processing
124
Program Example of Interrupt Processing
126
Delayed Interrupt Generation Module
130
Operation of Delayed Interrupt Generation Module
131
Chapter 4 Reset
132
Outline of Reset
133
Reset Factors and Oscillation Stabilization Wait Times
135
External Reset Pin
137
Reset Operation
138
Reset Factor Bit
140
State of each Pin at Reset
142
Chapter 5 Clock
144
Outline of Clock
145
Block Diagram of Clock Generation Section
147
Clock Select Register (CKSCR)
149
Clock Mode
151
Oscillation Stabilization Wait Time
153
Connection of Oscillator and External Clock
154
Chapter 6 Low-Power Consumption Mode
156
Outline of Low-Power Consumption Mode
157
Block Diagram of Low-Power Consumption Control Circuit
160
Low-Power Consumption Mode Control Register (LPMCR)
162
CPU Intermittent Operation Mode
165
Standby Mode
166
Sleep Mode
167
Time-Base Timer Mode
169
Stop Mode
170
State Transition Diagram
172
State of the Pin During Standby Mode, and Reset
174
Precautions When Using Low-Power Consumption Mode
175
Chapter 7 Mode Setting
178
Mode Setting
179
Mode Pins (MD2 to MD0)
180
Mode Data
181
Chapter 8 I/O Port
184
Functions of I/O Ports
185
I/O Port Register
186
Port Data Register (PDR0 to PDR2, PDR4 to PDR6)
187
Port Direction Register (DDR0 to DDR2, DDR4 to DDR6)
188
Other Registers
189
Chapter 9 Time-Base Timer
190
Overview of Time-Base Timer
191
Configuration of Time-Base Timer
193
Time-Base Timer Control Register (TBTC)
195
Interrupt of Time-Base Timer
197
Operations of Time-Base Timer
198
Precautions When Using Time-Base Timer
200
Program Example of Time-Base Timer
202
Chapter 10 Watchdog Timer
204
Overview of Watchdog Timer
205
Watchdog Timer Control Register (WDTC)
206
Configuration of Watchdog Timer
208
Operations of Watchdog Timer
209
Precautions When Using Watchdog Timer
211
Program Examples of Watchdog Timer
212
Chapter 11 Usb Function
214
Overview of USB Function
215
Block Diagram of USB Function
216
Registers of USB Function
217
UDC Control Register (UDCC)
220
EP0 Control Register (EP0C)
223
EP1 to EP5 Control Register (EP1C to EP5C)
225
Time Stamp Register (TMSP)
229
UDC Status Register (UDCS)
230
UDC Interruption Enable Register (UDCIE)
233
EP0I Status Register (EP0IS)
235
EP0O Status Register (EP0OS)
237
EP1 to EP5 Status Register (EP1S to EP5S)
240
EP0 to EP5 Data Register (EP0DT to EP5DT)
244
Operation Explanation of USB Function
245
Detecting Connection and Disconnection
248
Each Register Operation When Command Responds
250
STALL Response and Release
252
Suspend Function
256
Wake-Up Function
257
DMA Transfer Function
258
NULL Transfer Function
262
Fujitsu F2MC-16LX Series Hardware Manual (598 pages)
MB90470 Series 16-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 16.23 MB
Table of Contents
Table of Contents
9
Chapter 1 Overview of Mb90470
17
Overview
18
Block Diagram of MB90470
21
Package Dimensions
22
Pin Assignment
24
Pin Functions
26
I/O Circuit Type
32
Handling the Device
35
Chapter 2 Cpu
37
Overview of CPU Specifications
38
Memory Space
39
CPU Registers
43
Accumulator (A)
45
User Stack Pointer (USP) and System Stack Pointer (SSP)
46
Processor Status (PS)
47
Program Counter (PC)
50
Program Count Bank Register (PCB)
51
Direct Page Register (DPR)
52
General-Purpose Register (Register Bank)
53
Prefix Codes
54
Chapter 3 Interrupt
57
Overview
58
Interrupt Factor and Interrupt Vector
60
Interrupt Control Register and Peripheral Function
63
Interrupt Control Register (ICR00 to ICR15)
65
Interrupt Control Register Functions
68
Hardware Interrupt
71
Hardware Interrupt Operation
74
Flow of Hardware Interrupt Operation
76
Procedure for Using Hardwar Interrupt
77
Multiple Interrupts
79
Hardware Interrupt Processing Time
81
Software Interrupt
83
Interrupt by Μdma
85
DMA Descriptor
89
Individual Registers of DMA Descriptor
91
DMA Processing Procedure
94
Μdma Processing Time
95
Interrupt of Extended Intelligent I/O Service (EI 2 OS)
97
Extended Intelligent I/O Service
99
OS) Descriptor (ISD)
99
Description of Extended Intelligent I/O Service (EI 2 OS) Descriptor (ISD)
101
Operation of Extended Intelligent I/O Service (EI 2 OS)
104
Setting Procedure of Extended Intelligent I/O Service (EI 2 OS)
105
Processing Time for Extended Intelligent I/O Service (EI 2 OS)
106
Exception Processing Interrupt by Executing Undefined Instruction
109
Stack Operation of Interrupt Processing
110
Sample Program of Interrupt Processing
112
Delay Interrupt Event Module
115
Operation of Delay Interrupt Event Module
116
Chapter 4 Reset
117
Overview of Reset
118
Reset Factors and Oscillation Stabilization Wait Time
120
External-Reset Pin
122
Resetting
123
Reset-Factor Bits
125
Condition of Pins as Result of Reset
127
Chapter 5 Clocks
129
Overview
130
Block Diagram of Clock Generator
132
Clock Selection Register (CKSCR)
134
Clock Modes
137
Oscillation Stabilization Wait Time
141
Connecting Oscillator to External Clock
142
Chapter 6 Low-Power Consumption Mode
143
Overview of Low-Power Consumption Mode
144
Block Diagram of Low-Power Control Circuit
147
Low-Power Consumption Mode Control Register (LPMCR)
149
CPU Intermittent Operation Mode
152
Standby Mode
153
Sleep Mode
154
Timebase Timer Mode
156
Watch Mode
158
Stop Mode
160
State Transition Diagram
162
Pin State in Standby Mode, Hold, and Reset
164
Caution on Using Low-Power Consumption Mode
169
Chapter 7 Mode Setting
173
Mode Setting
174
Mode Pins (MD2 to MD0)
175
Mode Data
176
External Memory Access
180
Automatic Ready Function Selection Register (ARSR)
182
External Address Output Control Register (HACR)
184
Bus Control Signal Selection Register (EPCR)
185
Operation of each Mode for Mode Setting
187
External Memory Access Control Signals
188
Ready Function
191
Hold Function
194
Chapter 8 I/O Port
197
Functions of I/O Port
198
Registers for I/O Port
199
Port Registers (PDR0 to PDRA)
200
Port Direction Registers (DRR0 to DRRA)
201
Other Registers
203
Chapter 9 Timebase Timer
205
Overview
206
Timebase Timer Configuration
208
Timebase Timer Control Register (TBTC)
210
Timebase Timer Interrupt
212
Timebase Timer Operation
213
Notes on Using Timebase Timer
215
Sample Programs
217
Chapter 10 Watchdog Timer
219
Overview
220
Watchdog Timer Control Register (WDTC)
222
Watchdog Timer Configuration
224
Watchdog Timer Operation
226
Notes on Using Watchdog Timer
228
Sample Programs
229
Chapter 11 Watch Timer
231
Overview
232
Watch Timer Configuration
233
Watch Timer Control Register (WTC)
234
Watch Timer Operation
236
Fujitsu F2MC-16LX Series Hardware Manual (486 pages)
MB90550A/B Series, 16-BIT
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 7.3 MB
Table of Contents
Table of Contents
9
Chapter 1 Overview
17
Features
18
Available Models
21
Block Diagram
22
External Dimensions of the Package
23
Pin Assignment
25
Description of the Pin Functions
27
I/O Circuit Types
33
Cautions on Handling Devices
37
Chapter 2 Cpu
41
Memory Space
42
Addressing
43
Allocating Multiple-Byte Data in a Memory Space
46
Dedicated Registers
47
Accumulator (A)
49
User Stack Pointer (USP) and System Stack Pointer (SSP)
51
Processor Status (PS)
52
Program Counter (PC)
55
Direct Page Register (DPR)
56
Bank Registers (PCB, DTB, USB, SSB, ADB)
57
General-Purpose Registers
58
Prefix Codes
60
Interrupt Suppression Instructions and Prefix Codes
62
Notes on Using the "DIV A, Ri" and "DIVW A, Rwi" Instructions
63
Chapter 3 Interrupts
67
Overview of Interrupts
68
Interrupt Causes
69
Interrupt Vectors
72
Hardware Interrupts
74
Operation of Hardware Interrupts
77
Operating Flow for Hardware Interrupts
80
Example of Procedure for Using Hardware Interrupts
81
Software Interrupts
82
Expanded Intelligent I/O Service (EI 2 OS)
84
Interrupt Control Register (ICR)
86
Expanded Intelligent I/O Service Descriptor (ISD)
89
Operation of the Expanded Intelligent I/O Service (EI 2 OS)
93
Execution Time of the Expanded Intelligent I/O Service (EI 2 OS)
95
Exceptions Because of Executing Undefined Instructions
96
Chapter 4 Generating and Resetting Clocks
97
Clock Generator
98
Clock Supply Map
99
Reset Causes
100
Operation after a Reset Is Released
102
Registers Not Initialized by Reset Input
103
Chapter 5 Low-Power Consumption Control Circuit
105
Overview of the Low-Power Consumption Control Circuit
106
Low-Power Consumption Mode Control Register (LPMCR)
109
Clock Selection Register (CKSCR)
111
Operation of the Low-Power Consumption Control Circuit
114
Sleep Mode
116
Watch Mode
117
Stop Mode
119
Hardware Standby Mode
120
Pin Status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes
121
Intermittent CPU Operation Function
124
Setting the Oscillation Stabilization Time
125
Machine Clock
126
Chapter 6 Memory Access Modes
129
Memory Access Mode Overview
130
Mode Pins
131
Mode Data
132
Memory Space for each Bus Mode
133
External Memory Access (External Bus Pin Control Circuit)
136
Registers for External Memory Access (External Bus Pin Control Circuit)
137
Automatic Ready Function Selection Register (ARSR)
138
External Address Output Control Register (HACR)
140
Bus Control Signal Selection Register (ECSR)
141
Operation of the External Memory Access Control Signals
144
Ready Function
146
Hold Function
148
Chapter 7 I/O Ports
149
I/O Port Overview
150
I/O Port Block Diagram
151
I/O Port Registers
154
Port Data Registers (Pdrx)
156
Port Data Direction Registers (Ddrx)
158
Output Pin Register (ODR4)
159
Input Resistor Registers (RDR0 and RDR1)
160
Analog Input Enable Register (ADER)
161
Chapter 8 Time-Based Timer
163
Overview of the Time-Based Timer
164
Time-Based Timer Control Register (TBTC)
165
Time-Based Timer Operations
167
Fujitsu F2MC-16LX Series Hardware Manual (66 pages)
EMULATOR
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 0.52 MB
Table of Contents
Table of Contents
13
Chapter 1 Product Handling and Specifications
15
Checking Packed Components
16
Appearance and Part Names
17
General Specifications
19
RS-232C Port Specifications
20
USB Port Specifications
21
LAN Port Specifications
22
External Trigger Input Terminal Specifications
23
Program Execution Output Terminal Specifications
24
Power-On Debug Specifications
25
Options
27
Precautions about Possible Problems
29
Precautions on Handling the Product
30
Precautions on Use
33
Chapter 2 Connecting the Emulator
35
System Configuration
36
Connecting an Adapter Board
37
Connecting the User System
38
Connecting a Probe
42
Connecting a Host Machine
44
Connecting Test Equipment
45
Connecting the AC Adapter
46
Chapter 3 Operating the Emulator
47
Mounting an Evaluation MCU
48
Clock Supply
49
Emulator-Dedicated Power Supply Switching
52
User Port Power Supply Switching
54
Switching the C Pin Setting
55
User Data Bus Switching
56
Using the Setting Switches
58
Power-On Sequence
61
Power-Off Sequence
63
Fujitsu F2MC-16LX Series Application Note (23 pages)
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 1.37 MB
Table of Contents
Revision History
2
Warranty and Disclaimer
3
Contents
4
Introduction
5
Table of Contents
4
1 Overview
6
Features of MB2147-05 Low Cost In-Circuit Emulator
6
Features Compared to MB2141A/B, MB2147-01
7
2 Hardware Installation
8
State of Delivery
8
System Set-Up
9
System Configuration
10
Insert Evaluation Chip
10
Supply of Clocks to the Evaluation Chip
11
Example Configuration
13
3 Software Installation
14
Installation of Softune Workbench
14
Installation of Communication Interface Drivers
14
RS 232 Communication
14
USB Communication
14
4 Set-Up Debug Configuration
15
Configure Debug Set-Up
15
5 Appendix
22
Trouble Shooting
22
Fujitsu F2MC-16LX Series Application Note (14 pages)
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 0.13 MB
Table of Contents
Revision History
2
Warranty and Disclaimer
3
Contents
4
Table of Contents
4
1 Introduction
5
2 Preparation of the Swb
6
Creating a New Softune Workbench Project and Workspace and Adjust Workspace Settings
6
Create SWB Project/Workspace and Select .Abs-File to be Used
6
Adjust SWB Project/Workspace Settings for Re-Opening at SWB Start
8
Adjust SWB Project/Workspace Settings for Automatic Debugger Start at SWB Start
9
Setup Debug Environment
9
3 Calling the Softune Workbench
12
Calling the Softune Workbench from the DOS Command Line
12
4 How to Change Debugger Environment (E.g. Changing Automatic Testing)
13
Debug Environment and Debug Support Information File
13
Selecting the Debug Environment
13
Changing the Command Procedure Files
13
Fujitsu F2MC-16LX Series Operation Manual (26 pages)
Brand:
Fujitsu
| Category:
Computer Hardware
| Size: 0.48 MB
Table of Contents
Product Outline
5
Connecting the Product
8
System Configuration
8
Operating the Product
13
Fujitsu F2MC-16LX Series Application Note (13 pages)
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 0.95 MB
Table of Contents
Table of Contents
3
Introduction
4
Rules to Create a Good Layout
4
Crystal Oscillator Circuit
5
Power Supply Routing
6
Noise Reduction for General IO Pins
9
Function of Certain MCU Pins
10
EMI Measurement for LX16-Family
11
Fujitsu F2MC-16LX Series User Manual (14 pages)
PC Serial Programming Adapter Cable for Fujitsu Flash Microcontroller-F²MC-16LX/FR Family
Brand:
Fujitsu
| Category:
Computer Hardware
| Size: 0.15 MB
Fujitsu F2MC-16LX Series Operation Manual (10 pages)
LQFP-48P PROBE CABLE (NQPACK VERSION)
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 0.15 MB
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