Hardware Interrupt; Overview; Structure; Operation - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

7.4 Hardware Interrupt

7.4 Hardware Interrupt

7.4.1 Overview

In response to an interrupt request signal from an internal resource, the CPU pauses current program
execution and transfers control to the interrupt processing program defined by the user. This function is
called the hardware interrupt function. A hardware interrupt occurs when relevant conditions are satisfied
as a result of two operations: comparison between the interrupt request level and the value in the interrupt
level mask register of PS of the CPU, and hardware reference to the I flag value in PS. The CPU performs
the following processing when a hardware interrupt occurs:
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the
system stack.
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
Fetches the corresponding interrupt vector value and branches to the processing indicated by that
value.

7.4.2 Structure

Hardware interrupts are handled by the following three sections:
Internal resources ...................Interrupt enable and request bits: Used to control interrupt requests
Interrupt controller...................ICR:Assigns interrupt levels and determines the priority
CPU ........................................I and ILM:Used to compare the requested and current interrupt
The status of these sections are indicated by the resource control registers for internal resources, the ICR
for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three
sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC
FFFFFF in memory. These addresses are shared with software interrupts.
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7.4.3 Operation

An internal resource that has the hardware interrupt request function has an interrupt request flag and
interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the inter-
rupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The
interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt
enable flag indicates "enable," the resource issues an interrupt request to the interrupt controller.
When two or more interrupt requests are received at the same time, the interrupt controller compares the
interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that
request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request
with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined
by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is
smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates the interrupt
processing microcode after the currently executing instruction is completed. The CPU references the ISE
bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that
the ISE bit is 0 (interrupt), and activates the interrupt processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area
indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB,
84 Chapter 7: Interrupt
from resources.
levels of simultaneously requested interrupts.
levelsand to identify the interrupt enable status.
Microcode:Interrupt processing step
to
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MB90580 Series