Status Register Lower Byte (Strl) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3.8 Status register lower byte (STRL)

Status register lower byte (STRL)
Address: 000078
H
Read/write
Initial value
[bit 7] WDBF (Write data buffer full):
This flag indicates the status of the write data buffer (WDB).
0
1
This bit is set when WDB is full and cleared when at least one byte of data can be written into WDB.
[bit 6] RDBF (Read data buffer full):
This flag indicates the status of the read data buffer (RDB).
0 Read data buffer is not full
1 Read data buffer is full
This bit is set when RDB is full and cleared when at least one byte of data can be received and stored
in RDB.
[bit 5] WDBE (Write data buffer empty):
This flag indicates the status of the write data buffer (WDB).
0
1
This bit is set when WDB is empty and cleared when data is written into WDB. Writing '1' to WDBC in
command register CMRL will set this bit.
[bit 4] RDBE (Read data buffer empty):
This flag indicates the status of the read data buffer (RDB).
0
1
This bit is set when RDB is empty and cleared when data is received and stored in RDB. Writing '1' to
RDBC in command register CMRL will set this bit.
MB90580 Series
7 6 5
WDBF RDBF WDBE
(R) (R) (R)
(0) (0) (1)
Write data buffer is not full
Write data buffer is full
Write data buffer is not empty
Write data buffer is empty
Read data buffer is not empty
Read data buffer is empty
4 3 2
RDBE ST3 ST2
(R)
(R) (R)
(1)
(X) (X)
13.3 Registers and Register Details
1 0
ST1 ST0
(R) (R)
(X) (X)
Chapter 13: IE Bus
Bit Number
STRL
155