Asynchronous Mode; Figure 12.4.3A Transfer Data Format (Modes 0 And 1) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

12.4 Operations

12.4.3 Asynchronous mode

(1) Transfer data format
UART handles NRX (non return to zero) format data only. Figure 12.4.3a gives the data format.
SIN0, SOT0
As shown in Figure 12.4.3a, the transfer data always starts from the start bit ('L' level data), transfer is
based on the data bit length specified by the first LSB, and transfer ends at the stop bit ('H' level data).
When external clock is selected, ensure that the clock is input.
In normal mode (mode 0), the data length can be 7 or 8 bits. In multi-processor mode (mode 1), the data
length must be 8 bits. In multi-processor mode, no parity bit can be added. Instead, the A/D bit is always
added.
(2) Reception
Data is always received while '1' is written to the RXE bit (bit 9) of the SCR register.
When the start bit appears in the reception line, one frame of data is received according to the data
format determined by the SCR register. Once a frame has been received, an error flag is set if an error
has occurred, and the RDRF flag (bit 12 of the SSR register) is set. At that time, if '1' is written to the
RIE bit (bit 9) of the same SSR register, a reception interrupt is issued to the CPU. Check the flags of
the SSR register. Read the SIDR register if the reception has been normal. If an error has occurred,
take appropriate measures.
The RDRF flag is cleared when the SIDR register is read.
(3) Transmission
Transmission data is written into the SODR register when '1' is set in the TXE bit (bit 8) of the SSR
register. Then, if '1' is written to the TXE bit (bit 8) of the SCR register, transmission is performed.
When the data set in the SODR register is loaded into the transmission shift register and transmission
starts, the TDRE flag is set again and the next transmission data item can be set. At that time, if '1' is
written to the TIE bit (bit 8) of the same SSR register, a transmission interrupt is issued to the CPU,
requesting to set the transmission data in the SODR register.
The TDRE flag is cleared when data is written to the SODR register.
134 Chapter 12: UART
0 1 0 1 1
Start LSB
01001101
B

Figure 12.4.3a Transfer data format (modes 0 and 1)

0 0 1 0 1
MSB Stop
A/D Stop
is transferred.
1
(Mode 0)
(Mode 1)
MB90580 Series