Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 7

9.4 Operations ...................................................................................................................................112
9.4.1 External interrupts .............................................................................................................112
9.4.2 DTP operation ...................................................................................................................113
9.4.3 Switching between external interrupt and DTP requests ...................................................114
9.5 Notes on use ...............................................................................................................................115
9.5.1 Conditions on the externally connected peripheral when DTP is used .............................115
9.5.2 Recovery from standby ......................................................................................................115
9.5.3 External interrupt/DTP operation procedure ......................................................................115
9.5.4 External interrupt request level ..........................................................................................115
Chapter 10 Delayed Interrupt Generation Module .......................................................................................117
10.1 Outline .......................................................................................................................................117
10.2 Block Diagram ...........................................................................................................................117
10.3 Registers and Register Details ..................................................................................................117
10.4 Operations .................................................................................................................................118
10.4.1 Delayed interrupt occurrence ..........................................................................................118
10.5 Notes on operation ....................................................................................................................118
10.5.1 Delayed interrupt request lock .........................................................................................118
Chapter 11 Communication Prescaler ..........................................................................................................119
11.1 Outline .......................................................................................................................................119
11.2 Block Diagram ...........................................................................................................................119
11.3 Register and Register Details ....................................................................................................120
11.3.1 Clock Division Control Registers .....................................................................................120
11.4 Operations .................................................................................................................................121
Chapter 12 UART ............................................................................................................................................123
12.1 Outline .......................................................................................................................................123
12.2 Block Diagram ...........................................................................................................................124
12.3 Register and Register Details ....................................................................................................125
12.3.1 Serial Mode Register (SMR0/1/2/3/4) ..............................................................................126
12.3.2 Serial Control Register (SCR0/1/2/3/4) ...........................................................................128
12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) 130
12.3.4 Serial Status Register (SSR0/1/2/3/4) .............................................................................130
12.4 Operations .................................................................................................................................132
12.4.1 Operation modes .............................................................................................................132
12.4.2 UART clock selection ......................................................................................................132
12.4.3 Asynchronous mode ........................................................................................................134
12.4.4 CLK synchronous mode ..................................................................................................135
12.4.5 Interrupt occurrence and flag set timing ..........................................................................137
12.4.6 I2OS (Intelligent I/O service) ...........................................................................................139
12.4.7 Notes on use ..................................................................................................................139
12.4.8 Application .......................................................................................................................139
Chapter 13 IE Bus ...........................................................................................................................................141
13.1 Outline .......................................................................................................................................141
13.2 Block Diagram ...........................................................................................................................142
13.3 Registers and Register Details ..................................................................................................143
13.3.1 Command register upper byte (CMRH) ...........................................................................146
13.3.2 Command register lower byte (CMRL) ............................................................................148
13.3.3 Unit address register (MAWH, MAWL) ............................................................................150
13.3.4 Slave address register (SAWH, SAWL) ..........................................................................150
13.3.5 Mutliaddress, control bit set register (DCWR) .................................................................151
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