7.4 Hardware Interrupt
The time required for the CPU to execute the interrupt processing in steps
Interrupt start
Interrupt return
Table 7.4.3a Compensation values for interrupt processing cycle count
Address indicated by the stack pointer
External area, 8-bit data bus
External area, even-numbered address
External area, odd-numbered address
Internal area, even-numbered address
Internal area, odd-numbered address
I & IF & IE =1
ILM > IL
Fetching and decoding next
instruction
INT instruction?
Executing ordinary instruction
NO
String instruction
repetition
completed?
Updating PC
86
Chapter 7: Interrupt
:
24 + 6 x Table 7.4.3a machine cycles
:
15 + 6 x Table 7.4.3a machine cycles (RETI instruction)
YES
AND
NO
Saving PS, PC, PCB, DTB, ADB, DPR,
and A to SSP stack, and setting ILM=IL
YES
NO
YES
Figure 7.4.3b Hardware interrupt operation flow
Cycle count compensation value
I
:
Flag in CCR
ILM
:
CPU level register
IF
:
Internal resource interrupt request
IE
:
Internal resource interrupt enable flag
ISE
:
EI2OS enable flag
IL
:
Internal resource interrupt request level
S
:
Flag in CCR
NO
ISE = 1
Saving PS, PC, PCB, DTB, ADB, DPR,
and A to SSP stack, and setting I=0
and ILM=IL
S←1
Fetching interrupt vector
and
is shown below.
+4
+1
+4
0
+2
YES
Extended intelligent I/O
service
MB90580 Series