Registers And Register Details; Interrupt/Dtp Enable Register (Enir: Enable Interrupt Request Register) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

9.3 Registers and Register Details

9.3 Registers and Register Details
Interrupt/DTP enable register
Address : 000030
Read/write
Initial value
Interrupt/DTP cause register
Address : 000031
Read/write
Initial value
Request level setting register (Lower Byte)
Address : 000032
Read/write
Initial value
Request level setting register (Higher Byte)
Address : 000033
Read/write
Initial value

9.3.1 Interrupt/DTP enable register (ENIR: Enable interrupt request register)

Interrupt/DTP enable register
Address : 000030
Read/write
Initial value
ENIR enables the function to issue a request to the interrupt controller using a device pin as an external
interrupt/DTP request input. A pin corresponding to a '1' bit of this register is used as an external
interrupt/DTP request input. A pin corresponding to a '0' bit holds the external interrupt/DTP request input
cause, but does not issue a request to the interrupt controller.
110 Chapter 9: DTP/External Interrupt
7 6
H EN7 EN6 EN5
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14
ER7 ER6 ER5
H
(R/W) (R/W) (R/W)
(X) (X) (X)
7 6
LB3 LA3 LB2
H
(R/W) (R/W) (R/W)
(0) (0)
15 14 13
LB7 LA7 LB6
H
(R/W) (R/W) (R/W)
(0) (0)
7 6 5
H EN7 EN6 EN5
(R/W) (R/W) (R/W)
(0) (0) (0)
5 4 3
EN4 EN3 EN2
(R/W) (R/W) (R/W)
(0) (0) (0)
13 12 11
ER4 ER3 ER2
(R/W) (R/W) (R/W)
(X) (X) (X)
5 4 3
LA2 LB1 LA1
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
LA6 LB5 LA5
(R/W) (R/W) (R/W)
(0) (0) (0) (0)
4 3 2
EN4 EN3 EN2
(R/W) (R/W) (R/W)
(0) (0) (0)
2 1 0
EN1 EN0
ENIR
(R/W) (R/W)
(0) (0)
10 9 8
ER1 ER0
EIRR
(R/W) (R/W)
(X) (X)
2 1 0
LB0 LA0
ELVR (LOW)
(R/W) (R/W)
(0) (0) (0)
9 8
LB4 LA4
ELVR (HIGH)
(R/W) (R/W)
(0) (0)
1 0
EN1 EN0
ENIR
(R/W) (R/W)
(0) (0)
MB90580 Series
Bit number
Bit number
Bit number
Bit number
Bit number