Chapter 20 16-Bit I/O Timer; Outline - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Chapter 20:
16-Bit I/O Timer

20.1 Outline

The 16-bit I/O timer consists of a 16-bit free-run timer, two output compare modules, and four input capture
modules. The count values of this timer are used as the base timer for output compare and input capture.
Using this function, two independent waveforms can be output based on 16-bit free-run timer to enable
measurement of input pulse withs and external clock cycles.
• Four types of counter clock are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0, depending on the mode.
16-bit free-run timer (×1)
The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The 16-bit up
counter is used to counting up in synchronization to the machine clock, in which an interrupt factor can be
selected from the overflow interrupt and four types of timer intermediate bit interrupt to be operated as an
interval timer.
• Four types of counter clock are available.
Internal clock: ∅/4, ∅/16, ∅/32, ∅/64
• An interrupt can be generated upon a counter value overflow or a match with compare register 0.
(Compare match can be used only in an appropriate mode.)
• The counter value can be initialized to '0000H' upon a reset, software clear, or match with compare
register 0.
The free-run timer can be used to generating reference timing signals for the input capture (ICU) and
output compare (OCU).
Output compare (×2)
The output compare (OCU) consists of two 16-bit compare registers, compare output latch, and control
register.
An interrupt request can be generated for each channel upon a match detection by performing time-divi-
sion comparison between the OCU compare data register setting value and the counter value of the 16-bit
free-run timer.
When the 16-bit free-run timer value matches the compare register value, the output level is reversed and
an interrupt is issued.
• The four compare registers can be used independently.
Output pins and interrupt flags corresponding to compare registers
• Output pins can be controlled based on pairs of the four compare registers.
Output pins can be reversed by using the four compare registers.
• Initial values for output pins can be set.
• Interrupts can be generated upon a compare match.