5.2 Block diagram
5.2 Block diagram
TBTC
TBC1
TBC0
TBR
TBIE
TBOF
Timebase
interrupt
WDTC
WT1
WT0
WTE
WTC
WDCS
SCE
WTC1
WTC0
WTR
WTIE
WTOF
Clock
interrupt
WDTC
PONR
STBR
WRST
ERST
SRST
Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram
Figure 5.2a
52
Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
Selector
S
AND
Q R
Selector
AND
S
Q R
Selector
S
AND
Q R
12
2
Clock input
14
2
16
2
Timebase timer
18
2
TBTRES
14
16
2
2
Watchdog reset
2-bit counter
generation circuit
OF
CLR
CLR
10
2
10
2
2
13
2
14
2
Watch timer
15
2
WTRES
Main clock
17
18
2
2
To WDGRST
internal reset
generation
SCM
Power-on reset
/subclock stop
13
14
15
2
2
Clock input
Subclock
From power-on
generation
From hardware
standby control
circuit
RSTX pin
From RST bit of
STBYC register
MB90580 Series
circuit