Block Diagram; Figure 12.2A Block Diagram Of Uart - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

12.2 Block Diagram

12.2 Block Diagram
From
Communication
Prescaler
Baud rate
generator
Upper part of PPG timer
(PPG1)
External clock
SIN0/1/2/3/4
Reception status
judgment circuit
SMR0/1/2/3/4
register
124 Chapter 12: UART
Clock
Reception clock
selection
circuit
2
I OS reception error
signal (to CPU)
2
F MC-16LX BUS
MD1
MD0
SCR0/1/2/3/4
CS2
register
CS1
CS0
SCKE
SOE

Figure 12.2a Block diagram of UART

Transmission clock
Reception control
circuit
Start bit detect
circuit
Reception bit
counter
Reception parity
counter
Reception shifter
SIDR0/1/2
PEN
P
SSR0/1/2/3/4
SBL
CL
A/D
REC
RXE
TXE
Reception
interrupt
(to CPU)
SCK0/1/2/3/4
Transmission
interrupt
(to CPU)
Transmission control
circuit
Transmission
start circuit
Transmission bit
counter
Transmission
parity counter
SOT0/1/2/3/4
Transmission shifter
SODR0/1/2
PE
ORE
FRE
register
RDRF
TDRE
RIE
TIE
Control signal
MB90580 Series