Tbtc (Time Base Timer Control Register); Table 5.3.2A Selecting The Time Base Timer Interval - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5.3 Registers and register details

5.3.2 TBTC (Time Base Timer Control Register)

Timer base timer control register
Address: 0000A9
H
Read/write
Initial value
Note: Don't use read-modify-write command to access this register, otherwise malfunction
will occur.
[bit 15] Reserved
This is a reserved bit. When writing data to this register, ensure that '1' is written to this bit.
[bit 12] TBIE
This bit is used to enable interval interrupts based on the time base timer. Writing '1' to this bit enables
interrupts, and writing '0' disables interrupts. This bit is initialized to '0' upon a reset. This bit is readable
and writable.
[bit 11] TBOF
This is an interrupt request flag for the time base timer. While the TBIE bit is '1,' an interrupt request is
issued when '1' is written to TBOF. This bit is set to '1' for each interval specified with the TBC1 and
TBC0 bits.
This bit is cleared by writing '0,' by switching to stop or hardware standby mode, or by a reset. Writing
'1' has no effect.
1' is always read by a read-modify-write instruction.
[bit 10] TBR
This bit clears all bits of the time base timer counter to '0.'
Writing '0' clears the time base counter.
Writing '1' has no effect.
'1' is always read from this bit.
Note: Time base timer interrupt should be masked by either TBIE bit or ILM bit of CPU
before clearing the TBOF bit.
[bits 9 and 8] TBC1 and TBC0
These bits are used to set the time base timer interval.
TBC1
0
0
1
1
56 Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
15 14 13
Reserved
(-) (-) (-)
(1) (-) (-)

Table 5.3.2a Selecting the time base timer interval

TBC0
0
1
0
1
12 11
TBIE TBOF
(R/W) (R/W)
(0) (0)
Interval at 4 MHz
source oscillation
1.024 ms
4.096 ms
16.384 ms
131.072 ms
10 9 8
TBR TBC1 TBC0
(W) (R/W) (R/W)
(1) (0) (0)
Machine Clock Cycle
12
2 cycle
14
2 cycle
16
2 cycle
19
2 cycle
MB90580 Series
Bit number
TBTC