Multiaddress, Control Bit Read Register (Dcrr) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3.11 Multiaddress, control bit read register (DCRR)

Multiaddress, control bit read register (DCRR)
Address: 00007F
H
Read/write
Initial value
[bit 15-12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication bits):
In slave mode, the received multiaddress bit from the master is stored in bit DO0.
If the unit itself is the master, the multiaddress/normal communication set bits (DO3-0) in multiaddress,
control bit set register (DCWR) is read out.
Normal communction: (0001
Multiaddress communication: (0000
DO3~0 always read as "0".
[bit 11-8] C3, C2, C1, C0 (Control bits)
In slave mode, the received control bits from the master are stored in these bits.
If the unit itself is the master, the control bits (C3-0) in multiaddress, control bit set register (DCWR) is
read out. These bits are set after the control field has been received and acknowledge bit was detected.
For more detail description, please refer to Table 13.3.5a.
MB90580 Series
15 14 13
DO3 DO2 DO1
(R) (R) (R)
(0)
(0) (0)
)
B
B
12 11
DO0 C3
(R)
(R)
(X)
(X)
)
13.3 Registers and Register Details
10 9 8
C2 C1 C0
(R) (R) (R)
(X) (X) (X)
Chapter 13: IE Bus
Bit Number
DCRR
159