Chapter 4 Clock And Reset; Clock Generator; Figure 4.1A Clock Generator Circuit Block Diagram - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Chapter 4:
Clock and Reset

4.1 Clock Generator

The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and
PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is
called a machine cycle. A clock based on the source oscillation is called the main clock, and a clock based
on the internal VCO oscillation is called the PLL clock.
Note: When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz
and 16 MHz. The highest operating frequency for the CPU and peripheral resource
circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication
factor resulting in a higher frequency than 16 MHz is specified. For example, if the
source oscillation is 16 MHz, only 1 can be specified as the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation
below 4 MHz must not be specified.
Reset
Interrupt
HSTX
Transition to
stop mode
Selecting the oscillation
stabilization wait time
S Q
Transition to
S
Q
timer or
R
sleep mode
R
S Q
R
X0 XL

Figure 4.1a Clock generator circuit block diagram

Selecting the machine clock
1 2
PLL multiplication
Time base timer
1/2 1/2048 1/4
Selecting the watch-dog
timer interval
Machine clock
3 4
1/4 1/8
Monitoring
timer
Watch-dog reset