Write Data Buffer (Wdb); Table 13.3.14A Data Write Time After Wdb Empty Interrupt - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3 Registers and Register Details

13.3.14 Write data buffer (WDB)

Write data buffer (WDB)
Address: 000080
H
Read/write
Initial value
This register (internally is a 8-byte FIFO buffer) stored data to be transmitted in data field of the
communication frame. The data write interrupt timing is set by the two bits TIT1, TIT0 in command register
(CMRL).
When the write interrupt occurs, next data is requested to write into WDB. When all data has been trans-
mitted (WDB is empty), and the data cannot be writtenin RDB within the time listed in Table 13.3.14a, it
will result in an error and the transmission will be terminated. Writing '1' to WDBC bit in command register
CMRL will clear the buffer and return it as empty state.
This register can only be written when not full.
162 Chapter 13: IE Bus
7 6 5
WD7 WD6 WD5
(W) (W) (W)
(X) (X) (X)

Table 13.3.14a Data write time after WDB empty interrupt

Mode 0
Mode 1
Mode 2
4 3
WD4 WD3
(W) (W)
(X) (X)
Maximum Time
1580
400
290
2 1 0
WD2 WD1 WD0
(W) (W) (W)
(X) (X) (X)
No. of cycles
19000
4800
3400
MB90580 Series
Bit Number
WDB