Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 12

Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51
Figure 5.2a Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram ............................. 52
Figure 5.4.1a Watch-dog timer operation............................................................................................ 59
Chapter 6 Low Power Control Circuit .............................................................................................................61
Figure 6.2a Low-power consumption control circuit and clock generator ........................................... 62
Figure 6.4.8a Clock Selection State Transition Diagram (1) ............................................................... 72
Figure 6.4.8b Clock Selection State Transition Diagram (2) ............................................................... 73
Figure 6.4.9a Low Power Consumption Mode Transition Diagram A ................................................. 77
Figure 6.4.9b Low Power Consumption Mode Transition Diagram B ................................................. 78
Figure 6.4.9c Low Power Consumption Mode Transition Diagram C ................................................. 79
Figure 6.4.9d Low Power Consumption Mode Transition Diagram D ................................................. 80
Chapter 7 Interrupt ...........................................................................................................................................81
Figure 7.4.3a Occurrence and release of hardware interrupt ............................................................. 85
Figure 7.4.3b Hardware interrupt operation flow ................................................................................. 86
Figure 7.4.7a Registers saved in stack ............................................................................................... 87
Figure 7.5.3a Occurrence and release of software interrupt .............................................................. 89
Figure 7.6.1a Outline of extended intelligent I/O service .................................................................... 90
Figure 7.6.2a
Figure 7.6.3a EI2OS operation flow .................................................................................................... 97
Figure 7.6.3b EI2OS use flow ............................................................................................................. 98
Chapter 8 Parallel Ports .................................................................................................................................101
Figure 8.2a Block diagram of I/O port ............................................................................................... 102
Figure 8.2b Block diagram of input resistor register.......................................................................... 102
Figure 8.2c Block diagram of Output pin register .............................................................................. 102
Figure 8.3a Registers of Parallel Ports ............................................................................................. 103
Chapter 9 DTP/External Interrupt ..................................................................................................................109
Figure 9.2a Block diagram of DTP/External Interrupt ....................................................................... 109
Figure 9.4.1a External interrupt......................................................................................................... 112
Figure 9.4.2a Timing to cancel the external interrupt at the end of DTP operation........................... 113
Figure 9.4.2b Sample interface to the external peripheral ................................................................ 113
Figure 9.4.3a Switching between external interrupt and DTP requests ............................................ 114
Figure 9.5.4a Clearing the cause hold circuit upon level set............................................................. 115
Figure 9.5.4b Interrupt cause and interrupt request to the interrupt controller while
interrupts are enabled ........................................................................................................................ 115
Chapter 10 Delayed Interrupt Generation Module .......................................................................................117
Figure 10.2a Block diagram of Delayed Interrupt Generation Module .............................................. 117
Figure 10.4.1a Delayed interrupt issuance ....................................................................................... 118
Chapter 11 Communication Prescaler ..........................................................................................................119
Figure 11.2a Block diagram of Communication Prescaler ................................................................ 119
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Extended intelligent I/O service descriptor configuration ............................................ 94
MB90580 Series