Watch Timer Control Register (Wtc) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5.3.3 Watch Timer Control Register (WTC)

Watch timer control register
Address: 0000AA
H
Read/write
Initial value
[Bit 7] WDCS
This bit selects whether to use the clock signal from the watch timer or from the timebase timer for the
watchdog timer input clock when the main clock and PLL clock are selected. When this bit is "0", the
clock signal from the watch timer is selected; when this bit is "1", the clock signal from the timebase
timer is selected. In short, if WDCS is set to "1", then the timebase timer output can be selected if the
main clock and the PLL clock are selected, and the watch timer output can be selected if the subclock
is selected.
This bit is initialized to "1" by a power-on reset.
Note: When WDCS is set to "1", because the timebase timer output and the watch timer out-
put are asynchronous, there is a possibility that the watchdog timer count may
advance. Therefor, when WDCS is set to "1", it is necessary to clear the watchdog
timer before and after changing the clock mode.
[Bit 6] SCE
This bit indicates that the subclock oscillation stabilization waiting period has elapsed. When this bit is
"0", it indicates that the oscillation stabilization period is currently in progress.
stabilization period is fixed at 2
by stopping.
[Bit 5] WTIE
This bit enables interval interrupts by the watch timer. When this bit is set to "1", interrupts are enabled;
when set to "0", interrupts are disabled. This bit is initialized to "0" by a reset. This bit can be read and
written.
[Bit 4] WTOF
This bit is the watch timer interrupt request flag. When the WTIE bit is "1", an interrupt request is
generated if WTOF is set to "1". This bit is set to "1" at the intervals set by the WTC1 and WTC0 bits.
This bit is cleared by writing a "0", by switching to stop mode or hardware standby mode, and by a
reset. Writing "1" to this bit has no meaning.
When this bit is read by a read-modify-write instruction, a "1" is read.
[Bit 3] WTR
This bit clears all of the watch timer counter bits to "0". The clock counter is cleared by writing a "0" to
this bit. Writing "1" to this bit has no meaning. Reading this bit returns a "1".
[Bits 2, 1, 0] WTC2, WTC1, WTC0
These bits set the watch timer interval. The interval settings are shown in Table 5.3.3a. These bits are
initialized to "000" by a reset. These bits can be read and written.
When writing these bits, clear bit 4 (WTOF) at the same time.
MB90580 Series
7 6 5
WDCS SCE WTIE
(R/W) (R) (R/W)
(1) (X) (0)
14
cycles (subclock). This bit is initialized to "0" by a power-on reset and
Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
4 3 2
WTOF WTR WTC2
(R/W) (R/W) (R/W)
(0) (0) (0)
5.3 Registers and register details
1 0 Bit number
WTC1 WTC0 WTC
(R/W) (R/W)
(0) (0)
The oscillation
57