Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 331

(5) Register indirect (@RWj j = 0 to 3)
This format accesses the memory address indicated by the contents of the general-purpose register
RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits
16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are
indicated by ADB.
(6) Register indirect with post-incrementing (@RWj+ j = 0 to 3)
This format accesses the memory address indicated by the contents of the general-purpose register
RWj. After the operand operation, RWj is incremented by the data length of the operand (by 1 for a
byte, 2 for a word, and 4 for a long-word). When RW0/RW1 is used, bits 16 to 23 of the address are
indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is
used, bits 16 to 23 of the address are indicated by ADB. Note that if the post-incremented result is the
address of the register for which the increment specification was made, the value that is referenced
subsequently is the incremented value. In addition, in such a case, if the instruction was a write
instruction, the data written by the instruction is given priority, so the register that was to have been
incremented contains the write data in the end.
(7) Register indirect with displacement
This format accesses the memory address indicated by the sum of the contents of the general-purpose
register RWj and the displacement value. The displacement value can be one of two types, either a
byte or a word, and is added as a signed value. When RW0, RW1, RW4, or RW5 is used, bits 16 to 23
of the address are indicated by DTB; if RW3 or RW7 is used, bits 16 to 23 of the address are indicated
by SPB, and if RW2 or RW6 is used, bits 16 to 23 of the address are indicated by ADB.
(8) Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
This format accesses the memory address indicated by the sum of the contents of the general-purpose
register and either RW0 or RW1. Bits 16 to 23 of the address are indicated by DTB.
(9) Program counter indirect with displacement (@PC + disp16)
This format accesses the memory address indicated by the sum of the "instruction address + 4 +
disp16". The displacement value is a word length value. Bits 16 to 23 of the address are indicated by
PCB.
The operand address is generally regarded as "the next instruction address + disp16", but note that this
does not hold true for the instructions indicated below:
• DBNZ eam, rel
• DWBNZ eam, rel
• MOV eam, #imm8
• MOVW eam, #imm16
• CBNE eam, #imm8, rel
• CWBNE eam, #imm16, rel
MB90580 Series
(@RWi + disp8 i= 0 to 7/@RWj + disp16
B.1 Addressing
j = 0 to 3)
APPENDIX B: Instructions 311