Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 61

[bit 11]: HMBS
This bit specifies the bus size when an area between 800000
16-bit external data bus mode. The size is controlled as described below.
0
1
This bit is initialized to '1' upon a reset in external vector mode 2. In any other mode, this bit is
initialized to '0' upon a reset.
[bit 10]: WRE
This bit controls the output of the external write signal pin (WRHX and WRLX pins in 16-bit bus mode
and WRX pin in 8-bit bus mode) as described below.
0
1
In 8-bit external data bus mode, P33 is used as an I/O port regardless of the value of this register.
This bit is initialized to '0' upon a reset.
[bit 9]: LMBS
This bit specifies the bus size when an area between 002000
16-bit external data bus mode. The size is controlled as described below.
0
1
This bit is initialized to '1' upon a reset.
Note: In 16-bit bus mode, set P33 and P32 in input mode (set '0' in bits 3 and 2 of DDR3)
when enabling the WRHX and WRLX functions by the WRE bit. In 8-bit bus mode, set
P32 in input mode (set '0' in bit 2 of DDR3) when enabling the WRX function by the
WRE bit. Even if RDY or HRQ input is enabled by the RYE or HDE bit, the I/O port
function of the port is valid. Therefore, ensure that '0' (input mode) is written to the
DDR3 bit corresponding to the port.
MB90580 Series
16-bit bus size access [default in mode other than external vector mode 2]
8-bit bus size access [default in external vector mode 2]
I/O port (P33 and P32) operation (write signal output disabled) [default]
Write strobe signal (WRHX/WRLX or WRX) output enabled
16-bit bus size access [default]
8-bit bus size access
3.2 External Memory Access
and FFFFFF is externally accessed in
H H
and 7FFFFF is externally accessed in
H H
Chapter 3: Memory 41