Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 304

20.3 Registers and Register Details
20.3.3.2 Control status register
Input Capture Control Status Register ch0,1 & Ch2,3
Address: 000068
H
00006A
H
Read/write
Initial value
[bits 7 and 6] ICP1 and ICP0
These bits are used as input capture interrupt flags. '1' is written to this bit upon detection of a valid
edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can
be generated upon detection of a valid edge.
These bits are cleared by writing '0.' Writing '0' has no effect. '1' is always read by a read-modify-write
instruction.
* ICP0: Corresponds to input capture 0. ICP1: Corresponds to input capture 1.
[bits 5 and 4] ICE1 and ICE0
These bits are used to enable input capture interrupts. While '1' is written to these bits, an input capture
interrupt is generated when the interrupt flag (ICP0 or ICP1) is set.
* ICE0: Corresponds to input capture 0. ICE1: Corresponds to input capture 1.
[bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00
These bits are used to specify the valid edge polarity of an external input. These bits are also used to
enable input capture operation.
*EG01 and EG00: Correspond to input capture 0. EG11 and EG10: Correspond to input capture 1.
284 Chapter 20: 16-Bit I/O Timer
7 6 5
ICP1 ICP0 ICE1
R/W R/W R/W
0 0 0
0 No valid edge detection (default)
1 Valid edge detection
0 Interrupt disabled (default)
1 Interrupt enabled
EG11 EG10
Edge detection polarity
EG01 EG00
0 0 No edge detection (stop)
0 1 Rising edge detection
1 0 Falling edge detection
1 1 Both edge detection
4 3 2
ICE0 EG11 EG10
R/W R/W R/W
0 0 0
1 0 Bit Number
ICS01
EG01 EG00
ICS23
R/W R/W
0 0
(default)
MB90580 Series