Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 9

16.3 Registers and Register Details ..................................................................................................221
16.3.1 Control status registers (ADCS1 and ADCS2) ................................................................222
16.3.2 ADCR1 and ADCR0 (Data registers) ..............................................................................226
16.4 Operations .................................................................................................................................228
16.5 Notes on use .............................................................................................................................234
16.5.1 Other considerations ......................................................................................................234
Chapter 17 D/A Converter ..............................................................................................................................235
17.1 Outline .......................................................................................................................................235
17.2 Block Diagram ...........................................................................................................................236
17.3 Registers and Register Details ..................................................................................................237
17.3.1 DAT0/1 ( D/A data register) .............................................................................................238
17.3.2 DACR0/1 ( D/A control register) ......................................................................................238
17.4 Operations .................................................................................................................................239
Chapter 18 Pulse Width Counter (PWC) Timer ............................................................................................241
18.1 Outline .......................................................................................................................................241
18.2 Block Diagram ...........................................................................................................................242
18.3 Regiaters and Register Details ..................................................................................................243
18.3.1 PWC control status register (PWCSR) ............................................................................244
18.3.2 PWC data buffer register (PWCR) ...................................................................................249
18.3.3 Divide Ratio Control Register (DIVR) ..............................................................................250
18.3.4 PWC noise cancelling register (RNCR) ...........................................................................251
18.4 Operations .................................................................................................................................252
18.5 Precautions ...............................................................................................................................265
Chapter 19 Clock Monitor Function ..............................................................................................................267
19.1 Outline .......................................................................................................................................267
19.2 Block Diagram ...........................................................................................................................267
19.3 Registers and Register Details ..................................................................................................268
19.3.1 Clock output enable register (CLKR) ...............................................................................268
Chapter 20 16-Bit I/O Timer ...........................................................................................................................269
20.1 Outline .......................................................................................................................................269
20.2 Block Diagram ...........................................................................................................................271
20.2.1 Overall Block Diagram of 16-bit I/O Timer .......................................................................271
20.2.2 Block Diagram of 16-bit free-run timer .............................................................................272
20.2.3 Block Diagram of Output Comparison .............................................................................272
20.2.4 Block Diagram of Input Capture ......................................................................................273
20.3 Registers and Register Details ..................................................................................................274
20.3.1 16-bit free-run timer .........................................................................................................274
20.3.2 Output comparison ..........................................................................................................278
20.3.3 Input capture ....................................................................................................................282
20.4 Operations .................................................................................................................................285
20.4.1 16-bit free-run timer .........................................................................................................285
20.4.2 16-bit output compare ......................................................................................................286
20.4.3 16-bit input capture ..........................................................................................................287
20.5 Timing .......................................................................................................................................288
20.5.1 16-bit free-run timer count timing .....................................................................................288
20.5.2 Output compare timing ....................................................................................................289
20.5.3 Input capture input timing ................................................................................................290
Chapter 21 ROM Correction Module .............................................................................................................291
21.1 Outline .......................................................................................................................................291
MB90580 Series ix