Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 268

18.3 Regiaters and Register Details
[bits 2, 1, 0] MOD2, MOD1, MOD0 (MOD2, 1, 0)
These bits select the operation mode and the pulse edges for width counting.
MOD2 MOD1
0
0
0
0
1
1
1
1
After a reset: Initialized to "000
Readable and writable.
Note: Changing the setting after activating the timer is prohibited. Only write to these bits before
starting or after halting the timer.
Note: When continuous count mode is set for the settings marked with an asterisk (*), the divider
circuit for the internal count clock is not cleared when the count ends so as to accumulate the
number of edges. In all other modes, the divider circuit for the internal count clock is cleared
when the count ends.
248 Chapter 18: Pulse Width Counter (PWC) Timer
MOD0
0 0 Timer mode, no pulse output
0 1 Timer mode, pulse output enabled (using the POT pin): Reload mode only
Inter-edge pulse width count mode ( ⇑ or ⇓ to ⇓ or ⇑ )
1 0
1 1 Divided period count mode (using input divider)
Rising-edge to rising-edge count mode ( ⇑ to ⇑ ).
0 0
"H" pulse width count mode( ⇑ to ⇓ ).
0 1
"L" pulse width count mode( ⇓ to ⇑ ).
1 0
Falling-edge to falling-edge count mode ( ⇓ to ⇓ ).
1 1
".
B
Operation Mode/Count Edge Selection
(Initial value)
*
*
*
*
*
*
MB90580 Series