Chapter 6 Low Power Control Circuit; Outline - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Chapter 6:
Low Power Control Circuit

6.1 Outline

The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode,
pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock
mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the
PLL clock mode, all of the other operating modes are low power consumption modes.
In main clock mode and main sleep mode, only the main clock (main OSC oscillation clock) and the
subclock (sub OSC oscillation clock) operate. In these modes, the main clock divided by two is used as
the operation clock, the subclock (sub OSC oscillation clock) is used as the watch clock, and the PLL clock
(VCO oscillation clock) is stopped.
In subclock mode and sub sleep mode, only the subclock (sub OSC oscillation clock) operates. The
subclock is used as the operation clock, and the main clock and the PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU's operation clock is stopped, all clocks other than
the CPU clock operate.
In pseudo-watch mode, only the watch timer and the timebase timer operate.
In PLL watch mode, main watch mode, and sub-watch mode, only the watch timer operates. Only the
subclock is in operation in this mode; the main clock and the PLL clock are stopped. (The difference
among PLL watch mode, main watch mode, and sub-watch mode is that the operating mode upon recov-
ery from an interrupt is PLL clock mode, main clock mode, or subclock mode, respectively. There are no
differences in the watch mode operations.)
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to
retain data while consuming the least amount of power possible. (The difference between main stop mode
and sub stop mode is that the operating mode upon recovery from an interrupt is main clock mode or
subclock mode, respectively. There are no differences in the stop mode operations.)
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower
power consumption by reducing the execution speed of the CPU while supplying a high-speed clock to the
on-chip resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. The
selected clock divided by two is used as the machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for when
stop mode and hardware standby mode are released.