Table 6.3.1A Cg Bit Setting - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.3 Registers and register details
[Bit 4] RST
Writing a "0" to this bit generates an internal reset signal in three machine cycles. Writing a "1' to this
bit has no effect. When this bit is read, a "1" is returned.
[Bit 3] TMD
Writing a "0" to this bit changes the mode to watch mode. Writing a "1" to this bit has no effect. This bit
is set to "1" by a reset, wake-up from watch or stop mode. This bit is a write-only bit. When this bit is
read, "1" is always returned.
[Bits 2, 1] CG1, CG0
These bits set the number of clock pause cycles for the CPU intermittent operation function.
These bits are initialized to "00" by a reset due to power-on, hardware standby, or a reset by the
watchdog timer. These bits are not initialized by resets due to other sources. These bits can be read or
written.
CG1
0
0
1
1
[Bit 0] SSR
When this bit is set to "1", DRAMC self-refresh control is performed in sleep (main/PLL) mode, watch
mode, and stop mode. This bit is cleared to "0" by a refresh. This bit can be read and written.
SSR has no function if there is no DRAMC on chip.
Note:
64 Chapter 6: Low Power Control Circuit

Table 6.3.1a CG Bit Setting

CG0 Number of CPU clock pause cycles
0
1 9 cycles (CPU clock: resource clock = 1: approximately 3 to 4)
0 17 cycles (CPU clock: resource clock = 1: approximately 5 to 6)
1 33 cycles (CPU clock: resource clock = 1: approximately 9 to 10)
0 cycles (CPU clock = resource clock)
MB90580 Series