15.2 Block Diagram
15.2 Block Diagram
16
8
16
2
3
208
Chapter 15: 16-Bit Reload Timer (with Event Count Function)
16-bit reload register
16-bit down-counter
2
GATE
Clock selector
EXCK
φ
φ
φ
Prescaler
1
3
5
2
2
2
clear
Peripheral clock
Figure 15.2a Block Diagram of 16-Bit Reload Timer
Reload
UF
OUT
CTL.
CSL1
CSL0
Re-trigger
IN CTL
Output enable
3
MOD2
MOD1
MOD0
RELD
OUTE
OUTL
INTE
IRQ
UF
CNTE
Clear
2
I
OSCLR
TRG
Port (TIN)
Port (TOUT)
Serial baud rate (ch0)
A/DC (ch1)
MB90580 Series