Figure 6.4.8A Clock Selection State Transition Diagram (1) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.4 Operations
Machine clock initialization
The MCS bit and the SCS bit are not initialized by a reset caused by an external pin or the RST bit. After
other types of resets, these bits are each initialized to "1".
Figure 6.4.8a and Figure 6.4.8b show the clock selection state diagram.
Power on
Main
SCS=1, MSC=1
SCM=1,MCM=1
CS1/0=xx
⇒
Sub PLLx
SCS=1, MSC=0
SCM=0,MCM=1
CS1/0=xx
⇒
Main Sub
SCS=1, MSC=x
MCM=1
SCM=1
(1) MCS bit clear and SCS bit set
(2) Completion of PLL clock oscillation stabilization wait and CS1/0 = 00
(3) Completion of PLL clock oscillation stabilization wait and CS1/0 = 01
(4) Completion of PLL clock oscillation stabilization wait and CS1/0 = 10
(5) Completion of PLL clock oscillation stabilization wait and CS1/0 = 11
(6) MCS bit set and SCS bit clear
(7) PLL clock and main clock synchronization timing and SCS = 1
(8) PLL clock and main clock synchronization timing and SCS = 0
(9) Completion of main clock oscillation stabilization wait MCS = 0
72 Chapter 6: Low Power Control Circuit
(1)
(7)
(7)
(7)
(9)
(8)
(7)
(8)
(8)
(8)

Figure 6.4.8a Clock Selection State Transition Diagram (1)

⇒
(2)
Main PLLx
SCS=1, MSC=0
SCM=1,MCM=1
CS1/0=xx
⇒
PLL1 Main
SCS=0orMSC=1
SCM=1,MCM=0
CS1/0=00
⇒
PLL2 Main
SCS=0orMSC=1
SCM=1,MCM=0
CS1/0=01
⇒
PLL3 Main
SCS=0orMSC=1
(6)
SCM=1,MCM=0
CS1/0=10
⇒
PLL4 Main
SCS=0orMSC=1
(6)
SCM=1,MCM=0
CS1/0=11
(3)
PLL1 multiplier
SCS=1, MSC=0
(6)
(4)
SCM=1,MCM=0
CS1/0=00
PLL2 multiplier
SCS=1, MSC=0
(6)
SCM=1,MCM=0
CS1/0=01
(5)
PLL3 multiplier
SCS=1, MSC=0
SCM=1,MCM=0
CS1/0=10
PLL4 multiplier
SCS=1, MSC=0
SCM=1,MCM=0
CS1/0=11
MB90580 Series