Operation; Watch-Dog Timer; Figure 5.4.1A Watch-Dog Timer Operation - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5.4 Operation

5.4.1 Watch-Dog Timer

The watch-dog timer function enables detection of program surge.
If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the
watch-dog timer resets the system.
(1) Activation
The watch-dog timer is activated by writing '0' to the WTE bit of the WTC register while the watch-dog timer
is stopped. At the same time, the WT1 and WT0 bits are used to set the watch-dog timer reset interval.
Only the interval setting specified during activation is valid.
(2) Watch-dog counter
Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the
program. Writing '0' to the WTE bit of the WTC register clears the watch-dog counter. The watch-dog
counter consists of a two-bit counter which uses the carry signals of the time base counter as a clock
source. Therefore, the watch-dog reset time may become shorter than the setting if the time base counter
is cleared.
Figure 5.4.1a is a diagram of the watch-dog timer operation.
Time base
Watch-dog
WTE write
(3) Watch-dog stop
Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware standby, or
reset by watch-dog. Reset by an external pin or software merely clears the watch-dog counter without
stopping the watch-dog function.
(4) Others
The watch-dog counter is cleared by a reset, transition to sleep or stop mode, or hold acknowledgment
signal in addition to writing the WTE bit.
MB90580 Series
00 01
Watch-dog activation

Figure 5.4.1a Watch-dog timer operation

Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
10 00 01
Watch-dog clear
5.4 Operation
10 11 00
Watch-dog reset
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