Pwc Noise Cancelling Register (Rncr) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

18.3.4 PWC noise cancelling register (RNCR)

PWC Noise Cancelling register
Address : 000086
Read/write
Initial value
The PWC noise removal circuit is used for removing noises form the input signal. H level and L level
detection will be applied to the input signal after it was 'cleaned' by the noise filter.
Noise removal circuit is a digital low pass filter, the filter remove the high frequency components of the
input signal. The noise-removed signal is called 'RMCSIG'. This signal has the same polarilty with the
orginial input signal, but the there may be slight phase difference. The SW bits of the noise cancelling
register specifies the noise pulse width which can be removed by the filter circuit.
This noise cancelling register is a 8-bit register, when reset, all bits will be initialized to 0.
[bits 2, 1] SW1, SW0
SW1 and SW0 is the clock mode selection bit which specify the noise pulse width to be removed.
The timing of the following table assumes the main clock is 16MHz.
[bits 0] EN
EN bit is used for enabling this noise cancelling function.
MB90580 Series
7 6
—
—
H
(-) (-)
(-) (-)
SW1 SW0
0 0
0 1
1 0
1 1
0 Noise cancelling function disabled
1 Noise canncelling function enabled
5 4 3
— — —
(-) (-) (-) (R/W)
(-) (-) (-)
Input Clock
0.5 MHz
31.25 KHz
15.62 KHz
7.81 KHz
Chapter 18: Pulse Width Counter (PWC) Timer
18.3 Regiaters and Register Details
2 1 0
SW1 SW0 EN
(R/W) (R/W)
(0) (0) (0)
Noise Pulse
Width
2.0 µs
32.0 µs
64.0 µs
128.0 µs
(Initial value)
Bit number
RNCR
251