Operations; Delayed Interrupt Occurrence; Notes On Operation; Delayed Interrupt Request Lock - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

10.4 Operations

10.4 Operations

10.4.1 Delayed interrupt occurrence

When the CPU writes '1' to the relevant bit of DIRR by software, the request latch in the delayed interrupt
source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the
highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to
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the F MC-16 CPU. The F
request, and starts the hardware interrupt processing microprogram as soon as the current instruction is
completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt processing
routine for this interrupt is thus executed.
Delayed interrupt source module
DDIR
The interrupt cause is cleared and tasks are switched by writing '0' to the corresponding bit of DDIR in the
interrupt processing routine.

10.5 Notes on operation

10.5.1 Delayed interrupt request lock

This lock is set by writing '1' to the corresponding bit of DIRR, and is cleared by writing '0' to the same bit.
Therefore, interrupt processing is reactivated immediately after control returns from interrupt processing,
unless the software is designed so that the cause of the interrupt is cleared within the interrupt
processing routine.
118 Chapter 10: Delayed Interrupt Generation Module
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MC-16 CPU compares the ILM bit of its internal CCR register and the interrupt
Interrupt controller
WRITE
Other requests
ICR
yy
ICR
xx

Figure 10.4.1a Delayed interrupt issuance

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F MC-16CPU
IL
CMP
ILM
NTA
CMP
MB90580 Series