Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 13

Chapter 12 UART ............................................................................................................................................123
Figure 12.2a Block diagram of UART................................................................................................ 124
Figure 12.3a Registers of UART ....................................................................................................... 125
Figure 12.4.3a Transfer data format (modes 0 and 1) ...................................................................... 134
Figure 12.4.4a Transfer data format (mode 2) .................................................................................. 135
Figure 12.4.5a Timing to set PE, ORE, FRE, and RDRF (mode 0) .................................................. 137
Figure 12.4.5b Timing to set ORE, FRE, and RDRF (mode 1) ......................................................... 137
Figure 12.4.5c Timing to set ORE and RDRF (mode 2).................................................................... 138
Figure 12.4.5d Timing to set TDRE (modes 0 and 1)........................................................................ 138
Figure 12.4.5e Timing to set TDRE (mode 2) ................................................................................... 138
Figure 12.4.8a Sample system configuration in mode 1 ................................................................... 139
Figure 12.4.8b Flow chart of communication in mode 1.................................................................... 140
Chapter 13 IE Bus ...........................................................................................................................................141
Figure 13.2a Block Diagram of IE Bus .............................................................................................. 142
Figure 13.3a Registers of IE BUS (1/3)............................................................................................ 143
Figure 13.3b Registers of IE BUS (2/3)............................................................................................. 144
Figure 13.3c Registers of IE BUS (3/3) ............................................................................................. 145
Figure 13.5.4a When setting '1' on WDBC (Master side of master transmission) ............................ 186
Figure 13.5.4b When setting '0' on WDBC (Master side of master transmission) ............................ 187
Figure 13.5.5a Error happened on the Slave side when master transmission.................................. 188
Figure 13.5.5b Error happened on the Master side when master transmission................................ 189
Chapter 14 8/16-Bit PPG ................................................................................................................................191
Figure 14.2a 8-bit PPG ch0 block diagram ....................................................................................... 192
Figure 14.2b 8-bit PPG ch1 block diagram ....................................................................................... 193
Figure 14.3a Registers of 8/16-bit PPG ............................................................................................ 194
Figure 14.4a PPG output operation, output waveform ...................................................................... 202
Figure 14.4b 8+8 PPG output operation waveform........................................................................... 203
Figure 14.4c Write timing chart ......................................................................................................... 205
Figure 14.4d PRL write operation block diagram .............................................................................. 205
Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207
Figure 15.2a Block Diagram of 16-Bit Reload Timer......................................................................... 208
Figure 15.3a Registers of 16-Bit Reload Timer ................................................................................. 209
Figure 15.3.1a Timer Control Status Register................................................................................... 210
Figure 15.3.2a 16-Bit Timer Register and 16-Bit Reload Register .................................................... 213
Figure 15.4.1a Counter Activation and Operation ............................................................................. 214
Figure 15.4.2a Underflow Operation ................................................................................................. 215
Figure 15.4.3a Trigger Input Operation ............................................................................................. 216
Figure 15.4.3b Gate Input Operation ................................................................................................ 216
Figure 15.4.5a Output Pin Functions (1) ........................................................................................... 217
Figure 15.4.5b Output Pin Functions (2) ........................................................................................... 217
MB90580 Series xiii