Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 8

13.3.6 Telegraph length set register (DEWR) ............................................................................152
13.3.7 Status register upper byte (STRH) ..................................................................................153
13.3.8 Status register lower byte (STRL) ...................................................................................155
13.3.9 Lock read register (LRRH, LRRL) ...................................................................................157
13.3.10 Master address read register (MARH, MARL) ...............................................................158
13.3.11 Multiaddress, control bit read register (DCRR) ..............................................................159
13.3.12 Telegraph length read register (DERR) .........................................................................160
13.3.13 Read data buffer (RDB) .................................................................................................161
13.3.14 Write data buffer (WDB) ................................................................................................162
13.4 IEBus Communication Protocol ................................................................................................163
13.4.1 Overview ..........................................................................................................................163
13.4.2 Determining bus mastership (arbitration) ........................................................................164
13.4.3 Communication mode ......................................................................................................164
13.4.4 Communication address ..................................................................................................165
13.4.5 Multiaddress communication ...........................................................................................165
13.4.6 Transfer protocol .............................................................................................................166
13.4.7 Transmit data ...................................................................................................................170
13.4.8 Bit format .........................................................................................................................173
13.5 Operation ..................................................................................................................................174
13.5.1 IEBus control ...................................................................................................................174
13.5.2 Communication status .....................................................................................................177
13.5.3 Program flow example for IEBus controller .....................................................................179
13.5.4 Timing Diagram of Multiple Frame Transmission ............................................................186
13.5.5 Timing diaram of transmission data when an error is generated .....................................188
Chapter 14 8/16-Bit PPG ................................................................................................................................191
14.1 Outline .......................................................................................................................................191
14.2 Block Diagram ...........................................................................................................................192
14.3 Registers and Register Details ..................................................................................................194
14.3.1 PPG0 operation mode control register (PPGC0) ............................................................195
14.3.2 PPG1 operation mode control register (PPGC1) .............................................................197
14.3.3 PPG0, 1 output pin control register (PPGOE) .................................................................199
14.3.4 Reload register (PRLL/PRLH ) ........................................................................................200
14.4 Operations .................................................................................................................................201
Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207
15.1 Outline .......................................................................................................................................207
15.2 Block Diagram ...........................................................................................................................208
15.3 Registers and Register Details ..................................................................................................209
15.3.1 Timer control status register (TMCSR) ............................................................................210
15.3.2 TMR (16-bit timer register)/TMRLR (16-bit reload register) .............................................213
15.4 Operation ..................................................................................................................................214
15.4.1 Internal clock operation ...................................................................................................214
15.4.2 Underflow operation ........................................................................................................215
15.4.3 Input pin functions (for internal clock mode) ....................................................................216
15.4.4 External event counter .....................................................................................................216
15.4.5 Output pin functions .........................................................................................................217
15.4.6 Intelligent I/O service (I2OS) function and interrupts .......................................................217
15.4.7 Counter operation state ...................................................................................................218
Chapter 16 A/D Converter ..............................................................................................................................219
16.1 Outline .......................................................................................................................................219
16.2 Block Diagram ...........................................................................................................................220
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