Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 297

[bit 3] MODE
The MODE bit is used to set the initialization condition of the 16-bit free-run timer.
When '0' is set, the counter value can be initialized by a reset or a clear bit (bit 2: CLR).
When '1' is set, the counter value can be initialized by a match with compare register 0 in addition to a
reset and a clear bit (bit 2: CLR).
* The counter value is initialized where the count value is changed.
[bit 2] CLR
The CLR bit initializes the operating 16-bit free-run timer value to '0000.'
When '1' is set, the counter value is initialized to '0000.' Writing '0' has no effect. '0' is always read from
this bit. The counter value is initialized where the count value changes.
* To initialize the counter value while the timer is stopped, write '0000' to the data register.
[bits 1 and 0] CLK1 and CLK0
CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is updated
immediately after a value is written to these bits. Therefore, ensure that the output compare and input
capture operations are stopped before a value is written to these bits.
CLK1 CLK0
0
0
1
1
* ∅ = Machine clock
MB90580 Series
0 Initialization by reset or clear bit (default)
1 Initialization by reset, clear bit, or compare register 0
0 No effect (default)
1 The counter value is initialized to '0000.
∅=16 MHz
Count clock
∅/4
0
∅/16
1
∅/64
0
∅/256
1
∅=8 MHz
0.25 µs 0.5 µs
1 µs 2 µs
4 µs 8 µs
16 µs 32 µs
20.3 Registers and Register Details
∅=4 MHz ∅=1 MHz
1 µs 4 µs
4 µs 16 µs
16 µs 64 µs
64 µs 256 µs
Chapter 20: 16-Bit I/O Timer 277