Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 149

[bit 11> A/D (Address/data):
This bit is used to specify the data format of the frame to be sent or received in multi-processor asyn-
chronous communication mode (mode 1).
0 Data frame
1 Address frame
[bit 10] REC (Receiver error clear):
This bit is used to clear the SSR register error flags (PE, ORE, and FRE). Writing '1' to this bit is invalid.
'1' is always read from this bit.
[bit 9] RXE (Receiver enable):
This bit is used to control UART reception.
0 Disables reception.
1 Enables reception.
Note: If reception is disabled while data is being received (being input to the reception shift
register), reception is terminated when the reception of that frame is completed and
the reception data is stored in the reception data buffer (SIDR register).
[bit 8] TXE (Transmitter enable):
This bit is used to control UART transmission.
0 Disables transmission
1 Enables transmission.
Note: If transmission is disabled while data is being transmitted (being output from the trans-
mission register), transmission is terminated after all data in the transmission data
buffer (SODR register) has been output.
MB90580 Series
12.3 Register and Register Details
[initial value]
[initial value]
[initial value]
Chapter 12: UART 129