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D7
30H
Phase adjustment for CCD data slice
0000:min 〜 1000:center 〜 1111:max
INIT:88H
31H
Phase adjustment for WSS data slice
0000:min 〜 1000:center 〜 1111:max
INIT:84H
PROG
32H
D1/D2
detection
0：Manual
INIT:80H
1：Auto det.
33H
MGAINSL
Manual Gain
set for GCA
0：OFF
INIT:00H
1：ON
34H
Adjustment start phase of output pulse of CGP
1000：-1.185μｓ 〜 0000：±０ 〜 0111：+1.04μｓ
INIT:00H
35H
INIT:07H
36H
CGPOUTM
BUS̲DCOMTRP1
CGP OUT
control
0:auto
INIT:00H
1:forced ON
37H
BUS̲YNCCK
Y NOISE
INIT:00H
* : Every blank register must be set "0".
Feb./2005
D6
D5
CCDDLY
1STEP = 128fh
WSSDLY
1STEP = 128fh
BUS̲FBCLMOD
Time constant of theInternal
Manual set
feed back clamping
0：D1
00：Reference
1：D2
10：Small
CGP̲S
0000：Sync center + 3.7μs
DET4VAL
Threshold level for DET. 443
［1000:MIN 0000:CEN 0111:MAX]
BUS̲BFD2
DCOMB OUT
C Trap
0：OFF
1：ON
BUS̲YNCLV
BUS̲YNCGA
Y NOISE LIM
Y NOISE GAIN
0:4LSB
0:×1/2
1:8LSB
1:×1
D4
D3
CDECEV1[4]
fsc pull in
performance
0:Nornal
1:Wide
01：Large
11：Mid
MGAIN
Adjustment for GCA Gain
1000：-1.185μｓ 〜 0000：±０ 〜 0111：+1.04μｓ
0
BUS̲YNCON
BUS̲CKILLLV
Y NOISE
CKILL Gain
0:OFF
0:Center
1:ON
1:+3dB
D2
D1
ID1DLY
Phase adjustment for ID1 data slice
0000:min 〜 1000:center 〜 1111:max
1STEP = 128fh
YADFILON
FILON１
13.5M trap
IIR FILTER
for ADC
selection
0：OFF
0:FIL1
1：ON
1:FIL2
CGP̲W
Adjustment pulse width of CGP
0000：center ( 2μs)
SYNC TIP CLAMP２
VDMSKCHG
Clamp control
00：ON
1
01：OFF
BGCTR
BUS̲CNCLV
BUS̲CNCGA
C NOISE LIM
C NOISE GAIN
0:4LSB
0:×1/2
1:8LSB
1:×1
TC90101FG
D0
FILON0
IIR FILTER
ON/OFF
0:OFF
1:ON
10：AUTO１
11：AUTO２
BUS̲ENPIXOFF
Mute
0：ON
1：OFF
BUS̲CNCON
C NOISE
0:OFF
1:ON
19
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