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１． B lock Diagram
Clamp
Y
CVBS
C
Cb
Cr
２．Pin Layout
Analog Input I/F
NCO
DAC
Feb./2005
HD/VD
Sync Sep.
Timing
SW
27M
AGC
10bit ADC
27M
8bit ADC
27M
8bit ADC
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
BIASYAD
7 6
1.5
VRTYAD
7 7
YIN
7 8
VSSYAD
7 9
VRMYAD
8 0
2.5
CVBS IN
TC90101FG
8 1
VDDYAD
8 2
VRBYAD
8 3
BIASCAD
8 4
VRTCAD
8 5
8 6
CIN
VSSCAD
8 7
2.5
Cb IN
8 8
VDDCAD
8 9
VRBCAD
9 0
BIASRAD
9 1
VRTRAD
9 2
VSSRAD
9 3
2.5
Cr IN
9 4
VDDRAD
9 5
VRBRAD
9 6
9 7
VDDDA
2.5
9 8
DAOUT
9 9
VSSDA
2.5
BIASDA
3.3
100
1
2
3
4
5
6
7
8
9
42M
X8PLL
XO
42M
X'tal
D/A
Clock
reference
× 8
clock
Gene.
S/N detection
macrovision
CCD slice
ID1
WSS
3line
27M
comb
→ 4fsc
IIC-BUS
SCL SDA
出力I/F
Output I/F
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6 5 5
1.5
3.3
Top view
1.5
3.3
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
TC90101FG
Vertical
enhance
LTI
contrast adust
ITU-R656
delay adjust
encodｅ
ＡＣＣ
color decord
ＴＩＮＴ adjust
Color adjust
5 4
5 3
5 2 5 1
TESTM5
5 0
VDDIO1
4 9
CKOUT
4 8
3.3
YOUT0
4 7
4 6
YOUT1
VSSIO1
4 5
YOUT2
4 4
出力I/F
Output I/F
YOUT3
4 3
4 2
DVSS3
YOUT4
4 1
1.5
YOUT5
4 0
DVDD3
3 9
YOUT6
3 8
YOUT7
3 7
3 6
YOUT8
3 5
YOUT9
DVSS2
3 4
1.5
3 3
CSYNC IN
DVDD2
3 2
TESTM4
3 1
3 0
TESTM3
2 9
TESTM2
2 8
TESTM1
SCL
2 7
2 6
SDA
2 1
2 2
2 3
2 4
2 5
656/601
Format
2
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