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BUS address
14H：D7-D6 Selection for
external-sync
14H：D5
Sync Separation level
14H：D4-D3 Sync-tip-clamp-mode for
CVBS
14H：D2
Setup for V-sepa
14H：D1
V-sepa limit
14H：D0
Setup of Half-H-killer It count Half-H at the V period.
15H：D7-D2 Horizontal phase
reference
15H：D1
Picture MUTE
15H：D0
Cb and Cr MUTE
16H：D7-D5 Time constant 1 for HPLL
(Phase difference:big)
16H：D4-D0 Loop Gain 1 for HPLL
(Phase difference:big)
17H：D7-D5 Time constant 2 for HPLL
(Phase difference:middle)
17H：D4-D0 Loop Gain 2 for HPLL
(Phase difference:middle)
18H：D7-D5 Time constant 3 for HPLL
(Phase difference:small)
18H：D4-D0 Loop Gain 3 for HPLL
(Phase difference:small)
Feb./2005
Function
It select the input signal of Composite-SYNC-in of Pin-33.
[00]: OFF(Internal) Pin33 must be connect to GND.
[01]: External composite Sync mode (polarity: High)
[10]: External composite Sync mode (polarity: Low)
[11]: External V-Sync mode (polarity: High)
Level of Sync-sepa is set up.
Initial value is [0]:30%.
It set the control of clamp.
[00]: Sync tip clamp ON [01]: Sync tip clamp OFF
[10]: AUTO1(Sync-tip-clamping becomes activity, When it
[11]: AUTO2 (Sync-tip-clamping becomes activity, When it
Setup for V-sepa
0: Type 1
1: Type 2 (Type 2 is more effective than Type1.)
Limit of V-sepa is set up.
V-sepa becomes easy, when it is set up in 1/16.
But,Usually use with 0(1/8）.
[0]: OFF (Initial value)
[1]: ON (It is effective for top-curl problem of non-standard
signal.(VCR trick mode etc･･)
Reference-Horizontal-counter of internal is set up.
This register is reference timing for all of internal
function. Usually, it uses with 0[µs].
[0]: Normal [1]: Picture Mute ON
[0]: Normal [1]: Color signal Mute ON
It is time-constant of PLL.
It becomes active when the phase difference has big value.
Reference value: [010]
It is Loop-Gain of PLL.
It becomes active when the phase difference has big value.
Reference value: [01110]
It is time-constant of PLL.
It becomes active when the phase difference has middle value.
Reference value: [100]
It is Loop-Gain of PLL.
It becomes active when the phase difference has middle value.
Reference value: [01101]
It is time-constant of PLL.
It becomes active when the phase difference has small value.
(it means under stable.)
Reference value: [101]
It is Loop-Gain of PLL.
It becomes active when the phase difference has small value.
Reference value: [00110]
detect non-signal or pedestal has a big difference.
detect non-signal.
Contents
TC90101FG
24
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