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5. LC, LSI description
@-1 Block Diagram (ARM 610)
@ ARM610 (CPU) description
The ARM610
(CPU) is a 32-bit RISC microprocessor which is
equipped with an MMU (Memory Management Unit) and a 4KB cash
memory.
The ARM has input clocks FCLK and MCLK. MCLK signal is used in
the memory cycle of the ARM. In making access to the RAM or the
ROM, the access speed is at a high level in order to reduce the
difference in the access speed of the ARM. So the ARM must be
weighted. In this case, however, the ARM is not directly weighted, but
~
pea
eo
MCLK signal is extended via ASIC and memory access is performed.
.
The FCLK's 40MHz clock is divided into 20MHz by ASIC.
>) restour ea,
20MHz ARM system clock 7727772272222222722?
if
if
is gape
res 69)
NAME
DESCRIPTION
———a
'A (31:0)
'© | Address bus
aay
=
ABE
74|
| | Address bus enable
Bus Controls
i——
ial
ABORT
138}
|! | External abort
Memory
on
Intertace
owe
NBW
Not byte/word
Control Bus
WORD/BYTE selection
0 (31:0)
Data bus
Data bus
Functional Diagram
DBE
|_4| | | data bus enable
FCLK
139]
| | Fastclock input
CLOCKS
Se
a
NFIQ
131|
| | Not fast interrupt request. | Interrupts
uae
oe
NIRQ
132]
1 | Not interrupt request.
Interrupts
ell
a
Address
Lock
73| © [Locked operation.
Control Bus
=
aa
MCLK
| 140] 1 _| Memory
clock input.
ae
=a} ata bus
NMREQ
2|
© | Not memory request.
Interrues: D
0
naw.
|__saw | Contot
MSE
1] | | Memory request'
Bus Controls
ocx
bus
Sequential enable
teeser_,]
ALE
117|
| | Address latch enable.
_| Bus Controls
NRESET
|137| | | Not reset.
[Control Bus
NRW
71] 0 | Notreadiwrite
Control Bus
{ aa
anweio
[ag
=
rhaaleter
SEQ
3| © | Sequential address
Memory
La
[soour_, | intrtace
Interface
L
z
SNA
144|
| | Synchronous/not
CLOCKS
Asynchronous.
NTEST
13]
1 |Nottest.
DEVICE TEST
7
x00.
[eseorma >)
TCLK
53|
| |Testintertace reference
| DEVICE TEST
Ene: { —ss__,
re
clock
TO!
49|
| | Testinterface data input. | DEVICE TEST
[ eae
ESD SO
TOO
48|
O | Test interface data output. | DEVICE TEST
STAG
m0
TMS
52| 1 | Testinterface mode select | DEVICE TEST
=
[ as
NTRST
50|
1 | Testintertace reset.
DEVICE TEST
ee Se
NWAIT
143|
| | Not wait.
CLOCKS
voD
1 | Positive Supply
| POWER
vss
1 | Ground Supply
GND
TESTOUT
© | Test bus output
CHIP TEST
TESTIN
| | Test bus input
CHIP TEST
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