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Section IV
CLOCK PULSE
I
TO
I
Tl
I
T2
I
T3
I
T4
I
T5
I
T6
I
T7
I
T!f
I
SCM
SCL
10GE(B)
100
STC
FLAG FF
D 0-15*
CB FF
RPE FF
ABS FF
SRQ
NOTES:
____________
~r__l~
__________ __
1.
SHADING INDICATES THAT CONDITION DEPENDS
ON PRIOR OPERATIONS.
2.
AN ASTERISK INDICATES THAT ONLY LOGIC
1
BITS ARE ILLUSTRATED.
3.
THE SCM AND SCL SIGNALS ARE THOSE CORRES-
PONDING TO THE DATA CARD.
2032-5
Figure 4-4. STC Instruction and Resulting Disc System
Operations, Timing Chart
clears the RP flip-flop. The output of MC23B is false
because the "not" run signal is true. (The Run FF was reset
by the OTA/B instruction that preceded the STC
instruction.) The gated and inverted STC signal is also
forwarded to the command card, where it resets the RPE
and ABS flip-flops. (The resetting of the RP and RPE
flip-flops is meaningful only when a disc read operation is
initiated. )
4-57.
With the Flag FF in the set state, a true§9lsignal
is sent to the DMA system by the data card.
4-58.
Upon receipt of the SRQ signal, the DMA system
acquires from the computer memory the first word to be
written on the disc, and places the word on lOBO lines 15
through
O.
Then the DMA system furnishes the following
signals to the data card: SCM, SCL, IOGE(B), and 100.
Upon receiving these signals, "nand" gate MC84A on the
data card furnishes a clock input to the 116 through 10 FF's
of the input register, and the word on the lOBO lines is
loaded into the register. (Flip-flop 116 receives no input
from pin 73. The - 2 volts applied to resistor MC115R2
furnishes a logic 0 to the flip-flop.) DMA also generates a
CLF signal, resetting the Flag FF on the data card.
4-59.
No further operations take place until the correct
sector is reached on the disc. During this interval the
Control Bit FF on the data card remains set, and if an
LIA/B instruction acquires the disc status word, bit 0 of the
status word (the busy bit) will be logic 1. As noted earlier,
diodes CR1 and CR2 form the input elements of an "or"
gate, and if either the Control Bit FF or the Run FF is set,
bit 0 of the status word is logic 1.
4·60.
If
a CLC instruction addresses the data card while
the starting sector is being awaited, the Control Bit FF on
4·8
12606B
the data card will be cleared by a CLC signal, and the disc
operation will be aborted before any data is transferred.
This programmed abort does not set the ABS FF.
4·61.
DISC WRITING. Disc writing is described in para·
graphs 4·62 through 4·107.
4·62.
Sector Coincidence. Writing begins when the
starting sector is reached on the disc.
It
has been seen that
the address of this sector is placed in the .sector address
register by an OT A/B instruction.
It
has also been seen that
the current next·sector address is in the sector counter.
The contents of the register and counter are compared by
"and" gates and MC75A and B, MC105A through D,
MC95A through D, MC85A through D, on the command
card. These gates compare the set-side outputs of the
counter flip·flops with the reset·side outputs of the register
flip· flops. They also compare the reset·side outputs with
the set·side outputs of the register. When the numbers in
the counter and the register are unlike, one or more of the
"and" gates encounters coincidence, and furnishes a true
signal to one of the "nor" gates MC105E, MC95E, MC85E,
or MC75E. The outputs of the three "nor" gates are "or"
tied. Thus if the numbers in the counter and the register are
unlike, a false output is provided by the "nor" gates.
4·63.
When the numbers in the counter and register are
alike, none of the "and" gates encounters coincidence, all
inputs to the four "nor" gates are false, and the output of
these four gates becomes true.
4·64.
It
will be noted that "nor" gate MC75E receives
inputs from "and" gates MC75D and MC75C. These two
"and" gates are permanently connected to MC75E within
the integrated circuit that contains all the MC75 gates. To
prevent MC75D and MC75C from furnishing true signals to
MC75E, the inputs to the two "and" gates are connected to
ground.
4·65.
It
will also be noted that pin 11 inputs to
MC105E, MC95E, MC85E, and MC75E are connected
together, as also are the pin 12 inputs. By connecting the
pins in this way, with no signal or enable input applied to
them, the outputs of the three "nor" gates are caused to
"or" together.
4·66.
Sector Coincidence FF. When address coincidence
is encountered, the output of the four "nor" gates becomes
true. This true signal is applied to "nand" gate MC46A. The
two other inputs to this gate are the reset·side output of the
SCP FF, and the SC (inverted "not" SC) pulse. Figure 4·5
illustrates the signals applied to the gate. In the illustration,
"nand" gate input and output signals are identified by the
pin numbers of the gate.
4·67.
As the illustration shows, coincidence for "nand"
gate MC64A does not occur until one disc sector after
address coincidence takes place. The circuits are designed to
operate in this fashion because the. number in the sector
counter is one greater than the address of the sector under
the read/write heads.
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