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12606B
4-123_
When a binary 0 is received, "nand" gates MC34C
and MC34D are both disabled, and the clock pulse applied
to the RP FF, together with the true input at pin 12 of the
flip-flop, sets the RP FF. Subsequently, logic l's will again
have no affect on the RP FF; MC34C merely retains the set
condition of the flip-flop, and MC34D is disabled. However,
when another binary 0 is received, MC34C and MC34D are
both disabled, and the clock pulse toggles the RP FF.
4-124.
Operations continue in this fashion, with each
logic 0 toggling the flip-flop, until the 17 bits of the word
have been received. Because odd parity is used, there should
be an even number of logic O's in the word, and the RP FF
should be in the reset state at the end of the word.
However, if an odd number of O's was received, a parity
error occurred, and the RP FF will be set at the end of the
word. When the STR FF on the command card is placed in
the set condition at the end of the word, the RPE FF is
placed in the same condition as the RP FF. Thereafter, the
RPE FF remains set and the RP FF plays no further part in
the operation.
If
another parity error occurs, the RP FF
will be in the clear state at the end of a word. However, the
RPE FF is not reset because it is held
in
the set condition
by the false input furnished to its pin 10 by its own pin 8.
4-125.
When the read operation
is
completed, an LIA/B
instruction can acquire the disc status word, and bit 0 of
the word can be examined to determine whether a parity
error occurred.
4-126.
The RPE FF is reset the next time an STC
instruction initiates a disc operation. When this occurs, a
false input is applied to pin 13 of the RPE FF, making the
output from pin 8 true. With pin 8 true, the input to pin 10
is no longer effective in holding the flip-flop set.
4-127.
The disc read operation can be terminated either
by reading all words scheduled, or the operation can be
aborted. Termination procedures are the same as for disc
writing. After termination, flip-flops and registers on the
disc interface cards will
be
in the same condition as when
writing is terminated, except that the
DI
FF is in the reset
state.
4-128.
As in disc writing, a true condition of the "not"
RY signal or a false condition of the "not" ACL signal sets
the ABS FF. After completion of the read operation, an
LIA/B instruction allows examination of the state of the
flip-flop.
4-129.
LIAjB
INSTRUCTION.
4-130.
Functions of the LIA/B instruction have been
dealt with in appropriate places when discussing disc
writing and reading. Operation of the instruction as a
whole, as it pertains to the disc interface cards, will now be
presented.
Section IV
4·131.
When an LIA/B instruction using the command
card I/O select code is decoded, the appropriate SCM and
SCL signals become true at T2. (See figure 4-7.) Then,
when lOGE (B) and IOI become true, "and" gate MC27 A
on the command card experiences coincidence. The output
of this gate is furnished to other "and" gates which forward
the various bits of the disc status word to the lOBI lines. At
T5TS, these bits are placed in the computer A- or
B-register.
SCM
~
L
SCl
~
L
10GE(B)
•
I
101
lOBI 15-0*
STBA/STBB
n
NOTES:
1.
SHADING INDICATES THAT CONDITION DEPENDS
ON PRIOR OPERATIONS.
2.
AN ASTERISK INDICATES THAT ONLY lOGIC 1
BITS ARE IllUSTRATED.
3.
THE SCM AND SCl SIGNALS ARE THOSE COR-
RESPONDING TO THE COMMAND CARD.
2032-8
Figure 4-7. LlA/B Instruction and Resulting Disc System
Operations, Timing Chart
4-132.
Table 3-2 describes the significance of the various
parts of the status word.
4-133.
The "not" SC pulses which advance the sector
counter are asynchronous with respect to computer timing.
During T4 and T5, while the sector counter is being
sampled by an LIA/B instruction, a "not" SC pulse could
result in an arithmetic carry rippling down the counter.
This would cause an erroneous indication of the next-sector
address in the status word if corrective measures were not
taken. "Nand" gate MC24B on the command card prevents
difficulty from this source. When an LIA/B instruction is
not being performed, pin 5 of the gate receives a false
input, and the input to pin 2 of "nand" gate MC24A is
true. MC24A then functions simply as an inverter, and
allows normal advance of the sector counter. However,
during T4 and T5 of an LIAjB instruction, pin 5 of MC24B
is true.
If
no SC pulse is received during this T4-T5 time
period, the input to pin 1 of MC24A is true, the output of
MC24A is false, and MC24B is disabled by its pin 4. Since
the sector counter is not being advanced at this time, no
change in operation is needed or provided. Assume,
4-15
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