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12606B
4-44.
Other flip-flops and registers on the interface cards
could be either set or reset.
4-45.
When the command card is addressed by an LIA/B
instruction, no change is made in the state of flip-flops on
the interface cards. However, when disc reading or writing
is initiated, flip-flops are set or cleared as required to start
the operation, and the word counter and bit counter start
running.
4-46.
WRITE OPERATIONS.
4-47.
G ENE R A L. Disc writing requires that the
computer initialize the DMA system, then furnish a CW 4
word to the disc system by means of an OTA/B instruction
addressed to the command card. (The CW 4 word is
described in section III of this manual.) The computer then
initiates writing by executing an STC in,struction addressed
to the data card.
4-48.
OTA/B INSTRUCTION. The CW4 word specifies
whether a read or write operation will be performed, and
specifies the track and sector in which reading or writing
will start. (Refer to table 3-3.) When the OTA/B instruction
which supplies this word is executed, the T-register in the
computer is reset in the last half of computer time period
TO (see figure 4-3). Then, during T2, the instruction is read
from the core storage unit in the computer, and placed in
the T-register. The OTA/B instruction is decoded, and the
appropriate SCM and SCL signals become true. (There are
eight each of the SCM and SCL signals, corresponding to
the eight high-order and eight low-order octal digits of the
range of I/O select oodes that can be used. The signals
which become true are those that specify the I/O select
code of the command card.)
CLOCK PULSE
I
TO
I
T1
I
T2
I
T3
I
T4
I
T5
I
T6
I
T7
I
Tf,!
I
RST
~
n
MST
I I
TR15.!Il*
----.J
L
SCM
------.J
L
SCL
~
L
10GE(B)
~
I
100
RUN FF
ru//U/U/(I/1W'f/I/#@M'
lOBO 15-f,!*
TA 7-~*
.~
S 6-f,!*
~~~m
DIFF
W"~I.
NOTES:
1.
SHADING INDICATES THAT CONDITION DEPENDS
ON PRIOR OPERATIONS.
2.
AN ASTERISK INDICATES THAT ONLY LOGIC 1
BITS ARE ILLUSTRATED.
3.
THE SCM AND SCL SIGNALS
AR~
THOSE CORRES·
PONDING TO THE COMMAND CARD.
2032-4
Figure 4-3. OTA/B Instruction and Resulting
Disc
System
Operations, Timing Chart
Section IV
4-49.
At T3 the lOGE (B) and 100 signals come true.
With SCM, SCL, IOGE(B), and 100 all true, "nand" gate
MC15B on the command card furnishes a false output
during T4 which ensures that the Run FF is in the reset
condition. Also, pin *19 of the command card furnishes a
false "not" STA signal to pin *19 of the data card to ensure
that the Control Bit FF is reset. The resulting false CB
signal furnished to pin *W of the command card ensures, in
turn, that the SAC FF is reset.
4-50.
If
the Control Bit FF was in the set condition, a
prior disc read or write operation was in progress. Resetting
the Control Bit FF will immediately terminate the former
operation. The Run, and SAC FFs might also have been set,
hence the necessity for ensuring that they are in the reset
condition before a new operation is started.
4-51.
At T4, the computer places CW4 on lOBO lines 15
through O. The bit positions of CW4 retain their identifi-
cation when CW4 is places on the lines. That is, the bit in
position 15 of the A- or B-register is gated onto lOBO
line 15, the bit in position 14 of the register is gated onto
lOBO line 14, etc.
4-52.
The track address, on lOBO lines 13-7, is clocked
into the track address register on the data card by "nand"
gate MC84B.
(P~E).s~~_~!.¥,,_
unused,flip-flop T A 7 allowsJor ..
f:
future expansion in track capacity.) On the command card,
the sector address, furnished on lOBO lines 6 through 0, is
clocked into the sector address register by "nand" gate
MC14A. (This gate functions as a negative-logic "nor"
gate.) The loading of the track and sector address registers
takes place at T4.
4-53.
Also at T4, the DI FF on the command card is set
by the logic 1 on lOBO line 15. The logic 1 on lOBO
line 15 corresponds to the 1 in bit position 15 of the CW4
word. This 1 indicates that disc writing, rather than reading,
will be performed
4-54.
Although the OT A/B instruction is addressed to
the command card, the data on lOBO lines 13 through 7 is
loaded into the track address register on the data card. This
is made possible by the false STA input applied to pin *19
of the data card.
4-55.
STC
INSTRUCTION. When the computer
decodes the STC instruction which initiates disc writing,
SCM and SCL signals that address the data card become
true at the start of T2. (See figure 4-4.) Signal lOGE (B)
becomes true at T3, and the STC signal is true during T4.
The STC signal is furnished to the data card, where
it
sets
the Flag FF through "nand" gate MC14B. The output of
this gate also resets the data shift register.
4-56.
The STC signal, inverted and gated by "nand" gate
MC16B, also sets the Control Bit FF and resets the RP
flip-flop. To reset the RP flip-flop, the gated and inverted
STC signal is applied to pin 2 of "nand" gate MC123A. This
gate functions as a negative-logic "nor" gate, and when its
output becomes true the false output of "nor" gate MC23B
4-7
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