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12606B
sc
sc
SCP FF
SCP
MC46A
SAC FF
MC56B
RUN FF
MC46-2
MC46-13
MC46-1
MC46-12
MC56-5
MC56-4
MC56-3
MC56-6
u-
I
------------------~~
u
__________________
~r__
NOTE:
NOT TO SCALE HORIZONTALLY
2032-6
Figure 4-5. Sector Coincidence, Timing Chart
4-68.
The output of the SAC FF is applied to "and"
gate MC57 A. This gate is enabled when the computer
acquires the disc status word with an LIA/B instruction.
The instruction gates the lOBI lines into the A- or B-register
of the computer, and by examining the state of the lOBI
5 bit, the program can determine whether the SAC FF is
set.
4-69.
Run FF. As figure 4-5 shows, the SAC FF is set
by the first "not" SC pulse of the desired sector. The
output of this flip-flop is furnished to "nand" gate MC56B,
which allows the Run FF to be set by the second "not" 8C
pulse. MC56B also furnishes a false signal to inverter
MC55D, which forwards a true RFW signal to pin *U on
the data card. At this time, pins *T, *S, and *17 on the
data card are also receiving true inputs. (The "not" EWW
input to pins *S and *17 is true because the STR FF on the
command card is set.) When the RFW input to pin *U
becomes true, "nand" gate MC15B on the data card
experiences coincidence, and its output becomes false. As a
result, the output of "nand" gate MC124B on the data card
becomes true. (MC124B functions as a negative logic "nor"
gate.) The true output of MC124B causes the contents of
the input register on the data card to be gated into the data
shift register. This word, previously received from the DMA
system, will be the first word written on the disc. Also, the
WP FF is reset and the Flag FF is set.
4-70.
When the Flag FF is set,
it
forwards a true SRQ
signal to the DMA system. DMA responds by placing the
next word on the lOBO lines, and by generating CLF, 100,
IOGE(B), SCM, and 8CL signals. The SCM and SCL signals
Section IV
address the data card. The CLF signal, gated by "nand"
gate MC16C, resets the Flag FF. The 100 signal, gated by
"nand" gate MC16D, transfers the new word from the
lOBO lines into the input register on the data card.
4-71.
Returning to the Run FF, when it becomes set it
furnishes a true input to "nand" gate MC46C. One of the
other inputs to the gate is received from the set-side output
of the DI FF. This flip.flop is in the set condition when
writing takes place. The other input to MC46C is the "not"
TP signal received from the data card. If track protection
does not exist, "not" TP is true, and MC46C furnishes a
false output. As a result, transistor Q1 conducts, and the
"not" W signal changes from approximately +2.5 volts to
approximately +0.3 volts. Writing on the disc then starts.
4-72.
The reset output of the Run FF is furnished to
"nand" gate MC37B. As noted earlier, an LIA/B instruction
which acquires the disc status word enables "nand" gate
MC37B. This gate furnishes bit 0 of the status word. If the
Run FF or Control Bit FF (or both) is set, bit 0 of the disc
status word will be 1, indicating that the disc is busy.
4-73.
Write Control Operations. Figure 4-6 illustrates the
signals which control disc writing and reading. Included in
the illustration are bit values for typical data words. At the
beginning of each sector, the word counter and bit counter
are cleared by the second "not" SC pulse. When a "not" W
signal from the command card initiates a disc write
operation, "not" BC pulses start. The leading (negative-
going) edge of each of these steps the bit counter on the
command card, indicating that a bit has been written on the
disc. At the leading edge of the 15th pulse all positions at
the bit counter contain logic 1, and "nand" gate MC44B is
enabled. (The "nand" gate output is identified in figure 4-6
by its output pin, MC44-8.) With the "nand" gate output
negative, the leading edge of the next (16th) "not" BC
pulse (inverted) resets the WRD FF, indicating that 16 data
bits have been transferred. Also, the 16th "not" BC pulse
clears the bit counter. With the WRD FF reset, the STR FF
is reset by the trailing (positive·going) edge of the 16th
"not" BC pulse. Then, at the leading edge of the 17th
"not" BC pulse, the WRD FF is again set.
4·74.
The leading edge of the 17th pulse also attempts
to set FF BO of the bit counter. However, because of the
circuit delay in setting the WRD FF, and delay in MC44A
and MC45E, the reset condition of the WRD FF holds BO
in the reset state. (MC44A functions as a negative-logic
"not" gate.) With the WRD FF set and the STR FF reset,
coincidence occurs for "nand" gate MC104A on the
command card. (The output of this gate is identified in
figure 4-6 as MC104-6. Also shown in the illustration is
MC84-8, the corresponding gate-output for read
operations.) The false output of MC104A is forwarded to
pins *8 and *17 on the data card as the "not" EWW signal.
At this time, the input to pin *T on the data card is true
because the DI flip-flop is set, and the input to pin *U on
the data card is false because "nand" gate MC56B on the
command card is not enabled due to the reset condition of
the SCP FF. (Refer to figure 4-2_) On the data card, "nand"
4-9
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