Read Burst Timing; Write Burst Timing; Fast Ras To Cas Delay Clock Cycle Setting; Leadoff Timing - Motorola CPV5000 Installation And Reference Manual

Read burst timing

This option is only available in manual DRAM setup. This option controls the
read burst timings. The options are x444, x333 and x222. The slowest option
is x444. The option x222 is only available for EDO DRAM.

Write burst timing

This option is only available in manual DRAM setup. This option controls the
write burst timings. The options are x444, x333, and x222. The slowest option
is x444.

Fast RAS to CAS delay clock cycle setting

This option is only available in manual DRAM setup. This option controls the
delay between RAS and CAS. When disabled, the delay is three clock cycles.
When enabled, the delay is two clock cycles.

Leadoff timing

This option is only available in manual DRAM setup. There are four
parameters that are set by this option: Read Leadoff timing, Write leadoff
timing, RAS #pre-charge, and Refresh RAS assertion. There are four options;
7/6/3/4, 6/5/3/4, 7/6/4/5, and 6/5/4/5.

Speculative readoff

This option is only available in manual DRAM setup. The option, when
enabled, can improve leadoff performance by one clock cycle. The option,
when enabled, allows the DRAM controller to start a read request before the
memory request has been decoded by the TXC. If the cycle does not actually
target DRAM, the DRAM cycle is terminated.

Turnaround insertion

This option is only available in manual DRAM setup. When this option is
enabled, an extra clock cycle is inserted between back to back DRAM cycles.
When disabled, the TXC controls back to back DRAM cycles.
WinBIOS Setup types
7-17
7