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5Installing Options
5
System memory configurations
The CPV5000 provides four 72-pin SIMM sites for memory expansion,
organized as two memory banks. Each bank consists of two sockets providing
a 64-bit wide data path and eight parity bits. Memory timing requires 60 ns or
70 ns fast page mode devices.
The CPV5000 supports up to 256 MB of on-board FPM memory or up to 256
MB of on-board EDO memory in various configurations. EDO memory is
often used for improved performance with or without secondary cache. EDO
memory is available in a x32 SIMM and is non-parity. EDO and FPM cannot
be combined in the same bank. The BIOS automatically detects the memory
size and type.
With FPM memory, parity generation/checking is provided for each byte.
Additionally, the chip set provides single bit Error Checking and Correction
(ECC) and double bit detection.
Five SIMM sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, and 32 MB are
supported. Sockets 6 and 7 comprise bank 0, sockets 8 and 9 comprise bank 1.
A bank must be completely filled to be operable.
Table 5-1 lists memory configurations supported. The table lists memory
configurations using x36 FPM DRAM SIMMs. The CPV5000 also supports
x32 EDO DRAM SIMMs similarly.
5-1
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