Jtag Interface Design Guide - Huawei MU509 Hardware Migration Manual

HUAWEI 30 mm × 30 mm LGA Module
Hardware Migration Guide
Pin Interface Name
No.
72 JTAG_TDO
87 JTAG_TDI
93 JTAG_RTC
K
14 PS_HOLD
100/ RESIN_N/JT
47 AG_SRST_
N

2.8.2 JTAG Interface Design Guide

To facilitate fault location, it is recommended that you lead out JTAG signals from test
points. The LGA module must be reserved with JTAG test point interfaces for fault
analysis and location. The JTAG interface signals include the following signals.
Arrange test points according to the following relationship.
The following figure shows the connections of JTAG signal pins.
Issue 08 (2016-12-12)
MC509 MU509
CMOS 1.8 V
CMOS 1.8 V CMOS 1.8 V
CMOS 1.8 V (pin 100)
HUAWEI Proprietary and Confidential
Copyright © HUAWEI Technologies Co., Ltd.
MU609 ME209u- ME909u
526
JTAG_SRST_N
(pin 47) reset for
JTAG debugging
LGA Interface Differences
MU709 ME909s
Reserved CMOS
1.8 V
N
CMOS RESIN_
1.8 V (pin N (pin
100) 100)
40